Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix lrsc from last commit

This commit is contained in:
Dolu1990 2022-01-10 14:21:20 +01:00
parent f46ad43f39
commit da53de360f
2 changed files with 5 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/main/scala/vexriscv/ip/DataCache.scala
View File

@ -864,8 +864,9 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
val lrSc = withInternalLrSc generate new Area{
val reserved = RegInit(False)
when(io.cpu.writeBack.isValid && !io.cpu.writeBack.isStuck && request.wr){
reserved := False
when(io.cpu.writeBack.isValid && !io.cpu.writeBack.isStuck){
reserved setWhen(request.isLrsc)
reserved clearWhen(request.wr)
}
}

4
src/test/cpp/regression/main.cpp
View File

@ -898,6 +898,7 @@ public:
status.fs = 3;
pcWrite(pc + 4);
}
lrscReserved = false;
} break;
#endif
case 0x37:rfWrite(rd32, i & 0xFFFFF000);pcWrite(pc + 4);break; // LUI
@ -949,6 +950,7 @@ public:
dWrite(pAddr, size, (uint8_t*)&i32_rs2);
pcWrite(pc + 4);
}
lrscReserved = false;
}break;
case 0x13: //ALUi
switch ((i >> 12) & 0x7) {
@ -1107,9 +1109,7 @@ public:
int32_t src = i32_rs2;
int32_t readValue;
#ifdef DBUS_EXCLUSIVE
lrscReserved = false;
#endif
uint32_t pAddr;
if(v2p(addr, &pAddr, READ_WRITE)){ trap(0, 15, addr); return; }