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VexRiscv
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DataCache.withInternalLrSc reserved clearing fix

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Dolu1990 2022-01-10 13:39:41 +01:00 committed by GitHub
parent 34e5cafb75
commit f46ad43f39
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1 changed files with 3 additions and 3 deletions
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6
src/main/scala/vexriscv/ip/DataCache.scala
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@ -864,8 +864,8 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
val lrSc = withInternalLrSc generate new Area{
val reserved = RegInit(False)
when(io.cpu.writeBack.isValid && !io.cpu.writeBack.isStuck && request.isLrsc){
reserved := !request.wr
when(io.cpu.writeBack.isValid && !io.cpu.writeBack.isStuck && request.wr){
reserved := False
}
}
@ -1167,4 +1167,4 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
s1.invalidations := RegNextWhen((input.valid && input.enable && input.address(lineRange) === s0.input.address(lineRange)) ? wayHits | 0, s0.input.ready)
}
}
}
}