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VexRiscv
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Fix dynamic prediction RVC allignement

This commit is contained in:
Dolu1990 2018-06-04 20:03:08 +02:00
parent fc835f370e
commit 702db29edd
1 changed files with 9 additions and 1 deletions
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10
src/main/scala/vexriscv/plugin/Fetcher.scala
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@ -452,7 +452,10 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
val branchContext = branchStage.input(PREDICTION_CONTEXT) val branchContext = branchStage.input(PREDICTION_CONTEXT)
val moreJump = decodePrediction.rsp.wasWrong ^ branchContext.line.history.msb val moreJump = decodePrediction.rsp.wasWrong ^ branchContext.line.history.msb
historyWrite.address := branchStage.input(PC)(2, historyRamSizeLog2 bits) historyWrite.address := branchStage.input(PC)(2, historyRamSizeLog2 bits) + (if(pipeline(RVC_GEN))
((!branchStage.input(IS_RVC) && branchStage.input(PC)(1)) ? U(1) | U(0))
else
U(0))
historyWrite.data.history := branchContext.line.history + (moreJump ? S(-1) | S(1)) historyWrite.data.history := branchContext.line.history + (moreJump ? S(-1) | S(1))
val sat = (branchContext.line.history === (moreJump ? S(branchContext.line.history.minValue) | S(branchContext.line.history.maxValue))) val sat = (branchContext.line.history === (moreJump ? S(branchContext.line.history.minValue) | S(branchContext.line.history.maxValue)))
@ -562,6 +565,11 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
historyWrite.valid clearWhen(branchContext.hazard || !branchStage.arbitration.isFiring) historyWrite.valid clearWhen(branchContext.hazard || !branchStage.arbitration.isFiring)
ifGen(compressedGen)({
// val decompressionFalure = decompressor.output.
})
} }
} }
} }