All base instruction pass Riscv-Test (load/store not tested)
This commit is contained in:
parent
ad6964f0bb
commit
7065ed5d93
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@ -114,8 +114,6 @@ case class VexRiscvConfig(pcWidth : Int){
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object REGFILE_WRITE_VALID extends Stageable(Bool)
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object REGFILE_WRITE_DATA extends Stageable(Bits(32 bits))
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val SRC1_USE = REG1_USE
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val SRC2_USE = REG2_USE
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object SRC1 extends Stageable(Bits(32 bits))
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object SRC2 extends Stageable(Bits(32 bits))
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object SRC_ADD_SUB extends Stageable(Bits(32 bits))
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@ -144,6 +142,11 @@ class VexRiscv(val config : VexRiscvConfig) extends Component with Pipeline{
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stages ++= List.fill(6)(new Stage())
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val prefetch :: fetch :: decode :: execute :: memory :: writeBack :: Nil = stages.toList
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plugins ++= config.plugins
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//regression usage
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writeBack.input(config.INSTRUCTION) keep() addAttribute("verilator public")
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writeBack.input(config.PC) keep() addAttribute("verilator public")
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writeBack.arbitration.isValid keep() addAttribute("verilator public")
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}
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@ -232,9 +235,9 @@ class DecoderSimplePlugin extends Plugin[VexRiscv] with DecoderService {
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val decodedBits = Bits(stageables.foldLeft(0)(_ + _.dataType.getBitsWidth) bits)
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val defaultBits = cloneOf(decodedBits)
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assert(defaultValue == 0)
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defaultBits := defaultValue
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for(i <- decodedBits.range)
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defaultBits(i) := Bool(defaultValue.testBit(i))
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val logicOr = for((key, mapping) <- spec) yield Mux[Bits](((input(INSTRUCTION) & key.care) === (key.value & key.care)), B(mapping.value & mapping.care, decodedBits.getWidth bits) , B(0, decodedBits.getWidth bits))
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decodedBits := logicOr.foldLeft(defaultBits)(_ | _)
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@ -291,8 +294,8 @@ class NoPredictionBranchPlugin extends Plugin[VexRiscv]{
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SRC1_CTRL -> Src1CtrlEnum.RS,
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SRC2_CTRL -> Src2CtrlEnum.RS,
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SRC_USE_SUB_LESS -> True,
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SRC1_USE -> True,
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SRC2_USE -> True
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REG1_USE -> True,
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REG2_USE -> True
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)
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val jActions = List[(Stageable[_ <: BaseType],Any)](
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@ -300,14 +303,13 @@ class NoPredictionBranchPlugin extends Plugin[VexRiscv]{
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SRC1_CTRL -> Src1CtrlEnum.FOUR,
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SRC2_CTRL -> Src2CtrlEnum.PC,
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SRC_USE_SUB_LESS -> False,
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REGFILE_WRITE_VALID -> True,
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SRC2_USE -> True
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REGFILE_WRITE_VALID -> True
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)
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decoderService.addDefault(BRANCH_CTRL, BranchCtrlEnum.INC)
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decoderService.add(List(
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JAL -> (jActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.JAL)),
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JALR -> (jActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.JALR)),
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JALR -> (jActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.JALR, REG1_USE -> True)),
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BEQ -> (bActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.B)),
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BNE -> (bActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.B)),
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BLT -> (bActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.B, SRC_LESS_UNSIGNED -> False)),
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@ -388,7 +390,7 @@ class PcManagerSimplePlugin(resetVector : BigInt,fastFetchCmdPcCalculation : Boo
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arbitration.isValid := True
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//PC calculation without Jump
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val pc = Reg(UInt(pcWidth bits)) init(resetVector)
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val pc = Reg(UInt(pcWidth bits)) init(resetVector) addAttribute("verilator public")
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when(arbitration.isValid && !arbitration.isStuck){
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val pcPlus4 = pc + 4
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if(fastFetchCmdPcCalculation) pcPlus4.addAttribute("keep") //Disallow to use the carry in as enable
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@ -480,7 +482,7 @@ class DBusSimplePlugin extends Plugin[VexRiscv]{
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BYPASSABLE_EXECUTE_STAGE -> True,
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BYPASSABLE_MEMORY_STAGE -> True,
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MEMORY_ENABLE -> True,
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SRC1_USE -> True
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REG1_USE -> True
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)
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decoderService.addDefault(MEMORY_ENABLE, False)
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@ -491,9 +493,9 @@ class DBusSimplePlugin extends Plugin[VexRiscv]{
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LBU -> (stdActions ++ List(SRC2_CTRL -> Src2CtrlEnum.IMI, REGFILE_WRITE_VALID -> True)),
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LHU -> (stdActions ++ List(SRC2_CTRL -> Src2CtrlEnum.IMI, REGFILE_WRITE_VALID -> True)),
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LWU -> (stdActions ++ List(SRC2_CTRL -> Src2CtrlEnum.IMI, REGFILE_WRITE_VALID -> True)),
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SB -> (stdActions ++ List(SRC2_CTRL -> Src2CtrlEnum.IMS, SRC2_USE -> True)),
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SH -> (stdActions ++ List(SRC2_CTRL -> Src2CtrlEnum.IMS, SRC2_USE -> True)),
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SW -> (stdActions ++ List(SRC2_CTRL -> Src2CtrlEnum.IMS, SRC2_USE -> True))
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SB -> (stdActions ++ List(SRC2_CTRL -> Src2CtrlEnum.IMS, REG2_USE -> True)),
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SH -> (stdActions ++ List(SRC2_CTRL -> Src2CtrlEnum.IMS, REG2_USE -> True)),
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SW -> (stdActions ++ List(SRC2_CTRL -> Src2CtrlEnum.IMS, REG2_USE -> True))
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))
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}
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@ -646,7 +648,7 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind) extends Plugin[VexRiscv]
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import pipeline.config._
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val global = pipeline plug new Area{
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val regFile = Mem(Bits(32 bits),32)
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val regFile = Mem(Bits(32 bits),32) addAttribute("verilator public")
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}
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decode plug new Area{
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@ -745,7 +747,7 @@ class IntAluPlugin extends Plugin[VexRiscv]{
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REGFILE_WRITE_VALID -> True,
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BYPASSABLE_EXECUTE_STAGE -> True,
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BYPASSABLE_MEMORY_STAGE -> True,
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SRC1_USE -> True
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REG1_USE -> True
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)
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val nonImmediateActions = List[(Stageable[_ <: BaseType],Any)](
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@ -755,11 +757,11 @@ class IntAluPlugin extends Plugin[VexRiscv]{
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REGFILE_WRITE_VALID -> True,
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BYPASSABLE_EXECUTE_STAGE -> True,
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BYPASSABLE_MEMORY_STAGE -> True,
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SRC1_USE -> True,
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SRC2_USE -> True
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REG1_USE -> True,
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REG2_USE -> True
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)
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val otherAction = List(
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val otherAction = List[(Stageable[_ <: BaseType],Any)](
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LEGAL_INSTRUCTION -> True,
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REGFILE_WRITE_VALID -> True,
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BYPASSABLE_EXECUTE_STAGE -> True,
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@ -790,7 +792,7 @@ class IntAluPlugin extends Plugin[VexRiscv]{
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))
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decoderService.add(List(
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LUI -> (otherAction ++ List(ALU_CTRL -> AluCtrlEnum.SRC1)),
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LUI -> (otherAction ++ List(ALU_CTRL -> AluCtrlEnum.SRC1, SRC1_CTRL -> Src1CtrlEnum.IMU)),
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AUIPC -> (otherAction ++ List(ALU_CTRL -> AluCtrlEnum.ADD_SUB, SRC_USE_SUB_LESS -> False, SRC1_CTRL -> Src1CtrlEnum.IMU, SRC2_CTRL -> Src2CtrlEnum.PC))
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))
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}
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@ -837,7 +839,8 @@ class FullBarrielShifterPlugin extends Plugin[VexRiscv]{
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SRC2_CTRL -> Src2CtrlEnum.IMI,
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REGFILE_WRITE_VALID -> True,
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BYPASSABLE_EXECUTE_STAGE -> False,
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BYPASSABLE_MEMORY_STAGE -> True
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BYPASSABLE_MEMORY_STAGE -> True,
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REG1_USE -> True
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)
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val nonImmediateActions = List[(Stageable[_ <: BaseType],Any)](
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@ -846,7 +849,9 @@ class FullBarrielShifterPlugin extends Plugin[VexRiscv]{
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SRC2_CTRL -> Src2CtrlEnum.RS,
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REGFILE_WRITE_VALID -> True,
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BYPASSABLE_EXECUTE_STAGE -> False,
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BYPASSABLE_MEMORY_STAGE -> True
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BYPASSABLE_MEMORY_STAGE -> True,
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REG1_USE -> True,
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REG2_USE -> True
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)
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val decoderService = pipeline.service(classOf[DecoderService])
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@ -900,7 +905,7 @@ object TopLevel {
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)
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config.plugins ++= List(
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new PcManagerSimplePlugin(0, true),
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new PcManagerSimplePlugin(0, false),
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new IBusSimplePlugin,
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new DecoderSimplePlugin,
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new RegFilePlugin(SYNC),
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@ -915,6 +920,8 @@ object TopLevel {
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val toplevel = new VexRiscv(config)
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// toplevel.service(classOf[DecoderSimplePlugin]).bench(toplevel)
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@ -9,7 +9,32 @@
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#include <cstring>
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#include <string.h>
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uint8_t memory[1024 * 1024];
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class Memory{
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public:
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uint8_t* mem[1 << 12];
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Memory(){
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for(uint32_t i = 0;i < (1 << 12);i++) mem[i] = NULL;
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}
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~Memory(){
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for(uint32_t i = 0;i < (1 << 12);i++) if(mem[i]) delete mem[i];
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}
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uint8_t* get(uint32_t address){
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if(mem[address >> 20] == NULL) mem[address >> 20] = new uint8_t[1024*1024];
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return &mem[address >> 20][address & 0xFFFFF];
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}
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uint8_t& operator [](uint32_t address) {
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return *get(address);
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}
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/*T operator [](uint32_t address) const {
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return get(address);
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}*/
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};
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//uint8_t memory[1024 * 1024];
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uint32_t hti(char c) {
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if (c >= 'A' && c <= 'F')
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@ -27,7 +52,7 @@ uint32_t hToI(char *c, uint32_t size) {
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return value;
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}
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void loadHexImpl(string path) {
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void loadHexImpl(string path,Memory* mem) {
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FILE *fp = fopen(&path[0], "r");
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fseek(fp, 0, SEEK_END);
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uint32_t size = ftell(fp);
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@ -46,7 +71,7 @@ void loadHexImpl(string path) {
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switch (key) {
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case 0:
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for (uint32_t i = 0; i < byteCount; i++) {
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memory[nextAddr + i] = hToI(line + 9 + i * 2, 2);
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*(mem->get(nextAddr + i)) = hToI(line + 9 + i * 2, 2);
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//printf("%x %x %c%c\n",nextAddr + i,hToI(line + 9 + i*2,2),line[9 + i * 2],line[9 + i * 2+1]);
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}
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break;
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@ -88,7 +113,6 @@ uint32_t regFileWriteRefArray[][2] = {
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#define assertEq(x,ref) if(x != ref) {\
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printf("\n*** %s is %d but should be %d ***\n\n",TEXTIFY(x),x,ref);\
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error = 1; \
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throw std::exception();\
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}
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@ -97,14 +121,12 @@ class success : public std::exception { };
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class Workspace{
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public:
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Memory mem;
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string name;
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VVexRiscv* top;
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int i;
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int error;
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Workspace(string name){
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error = 0;
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this->name = name;
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top = new VVexRiscv;
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}
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@ -114,15 +136,17 @@ public:
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}
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Workspace* loadHex(string path){
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loadHexImpl(path);
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loadHexImpl(path,&mem);
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return this;
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}
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virtual void postReset() {}
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virtual void checks(){}
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void pass(){ throw success();}
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void fail(){ throw std::exception();}
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Workspace* run(uint32_t timeout = 1000){
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cout << "Start " << name << endl;
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Workspace* run(uint32_t timeout = 5000){
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// cout << "Start " << name << endl;
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// init trace dump
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Verilated::traceEverOn(true);
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@ -142,6 +166,7 @@ public:
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top->reset = 0;
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top->eval();
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postReset();
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try {
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// run simulation for 100 clock periods
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@ -151,8 +176,11 @@ public:
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if (top->iCmd_valid) {
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assertEq(top->iCmd_payload_pc & 3,0);
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//printf("%d\n",top->iCmd_payload_pc);
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uint8_t* ptr = memory + top->iCmd_payload_pc;
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iRsp_inst_next = (ptr[0] << 0) | (ptr[1] << 8) | (ptr[2] << 16) | (ptr[3] << 24);
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iRsp_inst_next = (mem[top->iCmd_payload_pc + 0] << 0)
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| (mem[top->iCmd_payload_pc + 1] << 8)
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| (mem[top->iCmd_payload_pc + 2] << 16)
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| (mem[top->iCmd_payload_pc + 3] << 24);
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}
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checks();
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@ -172,10 +200,12 @@ public:
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if (Verilated::gotFinish())
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exit(0);
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}
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cout << "timeout" << endl;
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fail();
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} catch (const success e) {
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printf("SUCCESS\n");
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cout <<"SUCCESS " << name << endl;
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} catch (const std::exception& e) {
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std::cout << e.what();
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cout << "FAIL " << name << endl;
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}
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@ -213,53 +243,68 @@ public:
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loadHex("../../resources/hex/" + name + ".hex");
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}
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virtual void checks(){
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virtual void postReset() {
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top->VexRiscv->prefetch_PcManagerSimplePlugin_pc = 0x800000bcu;
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}
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virtual void checks(){
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if(top->VexRiscv->writeBack_arbitration_isValid == 1 && top->VexRiscv->writeBack_input_INSTRUCTION == 0x00000073){
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uint32_t code = top->VexRiscv->RegFilePlugin_regFile[28];
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if((code & 1) == 0){
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cout << "Wrong error code"<< endl;
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fail();
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}
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if(code == 1){
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pass();
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}else{
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cout << "Error code " << code/2 << endl;
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fail();
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}
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}
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}
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};
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string riscvTestMain[] = {
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"rv32ui-p-add.hex",
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"rv32ui-p-addi.hex",
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"rv32ui-p-and.hex",
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"rv32ui-p-andi.hex",
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"rv32ui-p-auipc.hex",
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"rv32ui-p-beq.hex",
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"rv32ui-p-bge.hex",
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"rv32ui-p-bgeu.hex",
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"rv32ui-p-blt.hex",
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"rv32ui-p-bltu.hex",
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"rv32ui-p-bne.hex",
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"rv32ui-p-j.hex",
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"rv32ui-p-jal.hex",
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"rv32ui-p-jalr.hex",
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"rv32ui-p-or.hex",
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"rv32ui-p-ori.hex",
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"rv32ui-p-simple.hex",
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"rv32ui-p-sll.hex",
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"rv32ui-p-slli.hex",
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"rv32ui-p-slt.hex",
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"rv32ui-p-slti.hex",
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"rv32ui-p-sra.hex",
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"rv32ui-p-srai.hex",
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"rv32ui-p-srl.hex",
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"rv32ui-p-srli.hex",
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"rv32ui-p-sub.hex",
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"rv32ui-p-xor.hex",
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"rv32ui-p-xori.hex"
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"rv32ui-p-simple",
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"rv32ui-p-lui",
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"rv32ui-p-auipc",
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"rv32ui-p-jal",
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"rv32ui-p-jalr",
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"rv32ui-p-beq",
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"rv32ui-p-bge",
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"rv32ui-p-bgeu",
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"rv32ui-p-blt",
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"rv32ui-p-bltu",
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"rv32ui-p-bne",
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"rv32ui-p-add",
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"rv32ui-p-addi",
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"rv32ui-p-and",
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"rv32ui-p-andi",
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"rv32ui-p-or",
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"rv32ui-p-ori",
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"rv32ui-p-sll",
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"rv32ui-p-slli",
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"rv32ui-p-slt",
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"rv32ui-p-slti",
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"rv32ui-p-sra",
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"rv32ui-p-srai",
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"rv32ui-p-srl",
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"rv32ui-p-srli",
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"rv32ui-p-sub",
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"rv32ui-p-xor",
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"rv32ui-p-xori"
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};
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string riscvTestMemory[] = {
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"rv32ui-p-lb.hex",
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"rv32ui-p-lbu.hex",
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"rv32ui-p-lh.hex",
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"rv32ui-p-lhu.hex",
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"rv32ui-p-lui.hex",
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"rv32ui-p-lw.hex",
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"rv32ui-p-sb.hex",
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"rv32ui-p-sh.hex",
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"rv32ui-p-sw.hex"
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"rv32ui-p-lb",
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"rv32ui-p-lbu",
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"rv32ui-p-lh",
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"rv32ui-p-lhu",
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"rv32ui-p-lw",
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"rv32ui-p-sb",
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"rv32ui-p-sh",
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"rv32ui-p-sw"
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};
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@ -1,57 +1,39 @@
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[*]
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[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
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[*] Sun Mar 12 18:21:04 2017
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[*] Tue Mar 14 18:15:03 2017
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[*]
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[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/sim.vcd"
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[dumpfile_mtime] "Sun Mar 12 18:18:56 2017"
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[dumpfile_size] 105148
|
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[dumpfile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/rv32ui-p-jalr.vcd"
|
||||
[dumpfile_mtime] "Tue Mar 14 18:13:30 2017"
|
||||
[dumpfile_size] 7129488
|
||||
[savefile] "/home/spinalvm/Spinal/VexRiscv/src/test/cpp/testA/yolo.gtkw"
|
||||
[timestart] 156
|
||||
[timestart] 0
|
||||
[size] 1776 953
|
||||
[pos] -1 -1
|
||||
*-4.022038 200 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[pos] -1 -353
|
||||
*-4.722985 26 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[treeopen] TOP.
|
||||
[sst_width] 487
|
||||
[sst_width] 418
|
||||
[signals_width] 559
|
||||
[sst_expanded] 1
|
||||
[sst_vpaned_height] 279
|
||||
@28
|
||||
TOP.VexRiscv.decode_BRANCH_CTRL[1:0]
|
||||
TOP.VexRiscv.execute_BRANCH_SOLVED[1:0]
|
||||
TOP.VexRiscv.execute_input_BRANCH_CTRL[1:0]
|
||||
TOP.VexRiscv.execute_input_BRANCH_SOLVED[1:0]
|
||||
TOP.VexRiscv.decode_arbitration_isValid
|
||||
TOP.VexRiscv.decode_arbitration_isStuck
|
||||
TOP.clk
|
||||
TOP.iCmd_valid
|
||||
@22
|
||||
TOP.VexRiscv.decode_input_INSTRUCTION[31:0]
|
||||
TOP.VexRiscv.decode_input_PC[31:0]
|
||||
TOP.VexRiscv.iCmd_payload_pc[31:0]
|
||||
TOP.iCmd_payload_pc[31:0]
|
||||
@28
|
||||
TOP.VexRiscv.iCmd_ready
|
||||
TOP.VexRiscv.iCmd_valid
|
||||
TOP.iCmd_ready
|
||||
@22
|
||||
TOP.VexRiscv.iRsp_inst[31:0]
|
||||
TOP.VexRiscv.prefetch_PcManagerSimplePlugin_jump_pcLoad_payload[31:0]
|
||||
TOP.iRsp_inst[31:0]
|
||||
@28
|
||||
TOP.VexRiscv.prefetch_PcManagerSimplePlugin_jump_pcLoad_valid
|
||||
TOP.VexRiscv.prefetch_arbitration_isValid
|
||||
TOP.VexRiscv.fetch_arbitration_isValid
|
||||
TOP.VexRiscv.decode_arbitration_isValid
|
||||
TOP.VexRiscv.execute_arbitration_isValid
|
||||
TOP.VexRiscv.memory_arbitration_isValid
|
||||
TOP.VexRiscv.writeBack_arbitration_isValid
|
||||
TOP.VexRiscv.prefetch_arbitration_removeIt
|
||||
TOP.VexRiscv.fetch_arbitration_removeIt
|
||||
TOP.VexRiscv.decode_arbitration_removeIt
|
||||
TOP.VexRiscv.execute_arbitration_removeIt
|
||||
TOP.VexRiscv.memory_arbitration_removeIt
|
||||
TOP.VexRiscv.writeBack_arbitration_removeIt
|
||||
TOP.reset
|
||||
@29
|
||||
TOP.VexRiscv.writeBack_arbitration_isValid
|
||||
@22
|
||||
TOP.VexRiscv.writeBack_input_PC[31:0]
|
||||
@28
|
||||
TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_valid
|
||||
@22
|
||||
TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_payload_address[4:0]
|
||||
TOP.VexRiscv.writeBack_RegFilePlugin_regFileWrite_payload_data[31:0]
|
||||
@28
|
||||
TOP.VexRiscv.clk
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
||||
|
|
Loading…
Reference in New Issue