Hardware/VexRiscv
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A FPGA friendly 32 bit RISC-V CPU implementation
12 commits 39 branches 2 tags 15 MiB
Assembly 62%
Scala 26.9%
C++ 4.7%
C 3.8%
Tcl 1.2%
Other 1.3%
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Charles Papon 7065ed5d93 All base instruction pass Riscv-Test (load/store not tested)
2017-03-14 20:13:35 +01:00
project boot 2017-03-08 22:17:48 +01:00
src All base instruction pass Riscv-Test (load/store not tested) 2017-03-14 20:13:35 +01:00
.gitignore Pass verilator simple literal, add, jump 2017-03-12 20:12:40 +01:00
backup boot 2017-03-08 22:17:48 +01:00
build.sbt WIP 2017-03-11 00:34:49 +01:00
README.md boot 2017-03-08 22:17:48 +01:00

README.md

WIP