Default branch

7f2bccbef2 · Merge pull request #434 from goekce/master · Updated 2024-11-15 05:47:51 -05:00

Branches

dev

7fac668e38 · Fix CsrPlugin FPU access · Updated 2024-09-20 09:40:36 -04:00

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2cd19c89b1 · Revert unwanted push IBusDBusCachedTightlyCoupledRam · Updated 2024-04-04 04:49:48 -04:00

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5a179acef6 · vexRiscvConfig misa is back · Updated 2023-09-26 08:01:56 -04:00

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9fd127d6d9 · fix naming · Updated 2023-09-08 10:26:23 -04:00

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5f67075e30 · Fix FPU with F64 support, not removing mantissa precision from F32 #317 · Updated 2023-03-01 07:56:25 -05:00

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bbbfc7ee6b · fix too early · Updated 2023-02-19 03:55:52 -05:00

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692f604dd5 · Fix VexRiscvSmpClusterGen without linux debug minimal features · Updated 2023-02-08 05:28:21 -05:00

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6abc6ec194 · Fix VexRiscvSmpClusterGen linux less mhartid · Updated 2022-03-18 07:34:46 -04:00

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3bd940e89d · Briey add memoryDataWidth arguments · Updated 2021-10-01 05:42:04 -04:00

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551e76d244 · VexRiscvSmpCluster add a few options · Updated 2021-07-02 13:04:30 -04:00

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0a0998fcea · #176 fix typo · Updated 2021-04-22 08:02:46 -04:00

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530554d19c · fix fpu diagram · Updated 2021-03-16 09:52:57 -04:00

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ec507308e7 · fix cfu gen error · Updated 2021-03-04 14:29:33 -05:00

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fpu

0530d22a1d · sync · Updated 2021-03-04 10:06:18 -05:00

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7afe6cbef8 · Update .travis.yml · Updated 2021-02-05 08:51:55 -05:00

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d0a572de98 · Add openroad config · Updated 2020-07-07 19:37:10 -04:00

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smp

c12f9a378d · Fix inv regression · Updated 2020-06-20 07:18:46 -04:00

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44005ebf31 · update Synthesis results · Updated 2020-03-07 12:22:01 -05:00

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d241f35625 · Remove usages of implicit string to B/U/S · Updated 2020-02-15 04:10:04 -05:00

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390645e581 · SpinalHDL 1.3.8 · Updated 2020-01-29 17:20:35 -05:00

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