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Fix BmbToLitexDram coherency

This commit is contained in:
Dolu1990 2020-06-03 16:29:21 +02:00
parent db50f04653
commit 73f88e47cb
1 changed files with 8 additions and 1 deletions
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9
src/main/scala/vexriscv/demo/smp/Misc.scala
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@ -205,10 +205,17 @@ case class BmbToLiteDram(bmbParameter : BmbParameter,
val rspContext = cmdContext.queue(rdataFifoSize)
val rdataFifo = io.output.rdata.queueLowLatency(rdataFifoSize, latency = 1)
val writeTocken = CounterUpDown(
stateCount = rdataFifoSize*2,
incWhen = io.output.wdata.fire,
decWhen = rspContext.fire && rspContext.isWrite
)
val canRspWrite = writeTocken =/= 0
val canRspRead = CombInit(rdataFifo.valid)
rdataFifo.ready := unburstified.rsp.fire && !rspContext.isWrite
rspContext.ready := unburstified.rsp.fire
unburstified.rsp.valid := rspContext.valid && (rspContext.isWrite || rdataFifo.valid)
unburstified.rsp.valid := rspContext.valid && (rspContext.isWrite ? canRspWrite | canRspRead)
unburstified.rsp.setSuccess()
unburstified.rsp.last := True
unburstified.rsp.source := rspContext.source