CsrPlugin now implement a IWake interface
DebugPlugin now wake the CPU if a halt is asked to flush the pipeline
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@ -311,8 +311,11 @@ trait CsrInterface{
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trait IContextSwitching{
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trait IContextSwitching{
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def isContextSwitching : Bool
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def isContextSwitching : Bool
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}
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}
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trait IWake{
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def askWake() : Unit
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}
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class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor with ExceptionInhibitor with IContextSwitching with CsrInterface{
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class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor with ExceptionInhibitor with IContextSwitching with CsrInterface with IWake{
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import config._
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import config._
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import CsrAccess._
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import CsrAccess._
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@ -338,6 +341,10 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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var privilege : UInt = null
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var privilege : UInt = null
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var selfException : Flow[ExceptionCause] = null
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var selfException : Flow[ExceptionCause] = null
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var contextSwitching : Bool = null
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var contextSwitching : Bool = null
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var thirdPartyWake : Bool = null
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override def askWake(): Unit = thirdPartyWake := True
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override def isContextSwitching = contextSwitching
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override def isContextSwitching = contextSwitching
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object EnvCtrlEnum extends SpinalEnum(binarySequential){
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object EnvCtrlEnum extends SpinalEnum(binarySequential){
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@ -378,6 +385,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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override def setup(pipeline: VexRiscv): Unit = {
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override def setup(pipeline: VexRiscv): Unit = {
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import pipeline.config._
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import pipeline.config._
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thirdPartyWake = False
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val defaultEnv = List[(Stageable[_ <: BaseType],Any)](
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val defaultEnv = List[(Stageable[_ <: BaseType],Any)](
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)
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)
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@ -886,7 +895,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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import execute._
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import execute._
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//Manage WFI instructions
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//Manage WFI instructions
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val inWfi = False.addTag(Verilator.public)
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val inWfi = False.addTag(Verilator.public)
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val wfiWake = RegNext(interruptSpecs.map(_.cond).orR) init(False)
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val wfiWake = RegNext(interruptSpecs.map(_.cond).orR || thirdPartyWake) init(False)
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if(wfiGenAsWait) when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.WFI){
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if(wfiGenAsWait) when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.WFI){
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inWfi := True
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inWfi := True
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when(!wfiWake){
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when(!wfiWake){
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@ -246,6 +246,11 @@ class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount :
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}
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}
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if(pipeline.things.contains(DEBUG_BYPASS_CACHE)) pipeline(DEBUG_BYPASS_CACHE) := True
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if(pipeline.things.contains(DEBUG_BYPASS_CACHE)) pipeline(DEBUG_BYPASS_CACHE) := True
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}
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}
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val wakeService = serviceElse(classOf[IWake], null)
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if(wakeService != null) when(haltIt){
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wakeService.askWake()
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}
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}}
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}}
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}
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}
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}
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}
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