CsrPlugin now implement a IWake interface

DebugPlugin now wake the CPU if a halt is asked to flush the pipeline
This commit is contained in:
Charles Papon 2019-11-19 18:36:42 +01:00
parent 6d0d70364c
commit 7ae218704e
2 changed files with 16 additions and 2 deletions

View File

@ -311,8 +311,11 @@ trait CsrInterface{
trait IContextSwitching{ trait IContextSwitching{
def isContextSwitching : Bool def isContextSwitching : Bool
} }
trait IWake{
def askWake() : Unit
}
class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor with ExceptionInhibitor with IContextSwitching with CsrInterface{ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with ExceptionService with PrivilegeService with InterruptionInhibitor with ExceptionInhibitor with IContextSwitching with CsrInterface with IWake{
import config._ import config._
import CsrAccess._ import CsrAccess._
@ -338,6 +341,10 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
var privilege : UInt = null var privilege : UInt = null
var selfException : Flow[ExceptionCause] = null var selfException : Flow[ExceptionCause] = null
var contextSwitching : Bool = null var contextSwitching : Bool = null
var thirdPartyWake : Bool = null
override def askWake(): Unit = thirdPartyWake := True
override def isContextSwitching = contextSwitching override def isContextSwitching = contextSwitching
object EnvCtrlEnum extends SpinalEnum(binarySequential){ object EnvCtrlEnum extends SpinalEnum(binarySequential){
@ -378,6 +385,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
override def setup(pipeline: VexRiscv): Unit = { override def setup(pipeline: VexRiscv): Unit = {
import pipeline.config._ import pipeline.config._
thirdPartyWake = False
val defaultEnv = List[(Stageable[_ <: BaseType],Any)]( val defaultEnv = List[(Stageable[_ <: BaseType],Any)](
) )
@ -886,7 +895,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
import execute._ import execute._
//Manage WFI instructions //Manage WFI instructions
val inWfi = False.addTag(Verilator.public) val inWfi = False.addTag(Verilator.public)
val wfiWake = RegNext(interruptSpecs.map(_.cond).orR) init(False) val wfiWake = RegNext(interruptSpecs.map(_.cond).orR || thirdPartyWake) init(False)
if(wfiGenAsWait) when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.WFI){ if(wfiGenAsWait) when(arbitration.isValid && input(ENV_CTRL) === EnvCtrlEnum.WFI){
inWfi := True inWfi := True
when(!wfiWake){ when(!wfiWake){

View File

@ -246,6 +246,11 @@ class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount :
} }
if(pipeline.things.contains(DEBUG_BYPASS_CACHE)) pipeline(DEBUG_BYPASS_CACHE) := True if(pipeline.things.contains(DEBUG_BYPASS_CACHE)) pipeline(DEBUG_BYPASS_CACHE) := True
} }
val wakeService = serviceElse(classOf[IWake], null)
if(wakeService != null) when(haltIt){
wakeService.askWake()
}
}} }}
} }
} }