More bus doc #266
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README.md
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README.md
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@ -868,6 +868,41 @@ Simple and light multi-way instruction cache.
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Note: If you enable the twoCycleRam option and if wayCount is bigger than one, then the register file plugin should be configured to read the regFile in an asynchronous manner.
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Note: If you enable the twoCycleRam option and if wayCount is bigger than one, then the register file plugin should be configured to read the regFile in an asynchronous manner.
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The memory bus is defined as :
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```scala
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case class InstructionCacheMemCmd(p : InstructionCacheConfig) extends Bundle{
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val address = UInt(p.addressWidth bit)
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val size = UInt(log2Up(log2Up(p.bytePerLine) + 1) bits)
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}
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case class InstructionCacheMemRsp(p : InstructionCacheConfig) extends Bundle{
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val data = Bits(p.memDataWidth bit)
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val error = Bool
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}
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case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle with IMasterSlave{
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val cmd = Stream (InstructionCacheMemCmd(p))
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val rsp = Flow (InstructionCacheMemRsp(p))
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override def asMaster(): Unit = {
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master(cmd)
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slave(rsp)
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}
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}
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```
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The address is in byte and aligned to the bytePerLine config, the size will always be equal to log2(bytePerLine).
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Note that the cmd stream transaction need to be consumed before starting to send back some rsp transactions (1 cycle minimal latency)
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Some documentation about Stream here :
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https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Libraries/stream.html?highlight=stream
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Flow are the same as Stream but without ready signal.
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#### DecoderSimplePlugin
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#### DecoderSimplePlugin
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This plugin provides instruction decoding capabilities to other plugins.
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This plugin provides instruction decoding capabilities to other plugins.
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@ -1046,6 +1081,75 @@ Multi way cache implementation with writh-through and allocate on read strategy.
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You can invalidate the whole cache via the 0x500F instruction, and you can invalidate a address range (single line size) via the instruction 0x500F | RS1 << 15 where RS1 should not be X0 and point to one byte of the desired address to invalidate.
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You can invalidate the whole cache via the 0x500F instruction, and you can invalidate a address range (single line size) via the instruction 0x500F | RS1 << 15 where RS1 should not be X0 and point to one byte of the desired address to invalidate.
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The memory bus is defined as :
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```scala
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case class DataCacheMemCmd(p : DataCacheConfig) extends Bundle{
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val wr = Bool
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val uncached = Bool
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val address = UInt(p.addressWidth bit)
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val data = Bits(p.cpuDataWidth bits)
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val mask = Bits(p.cpuDataWidth/8 bits)
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val size = UInt(p.sizeWidth bits) //... 1 => 2 bytes ... 2 => 4 bytes ...
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val exclusive = p.withExclusive generate Bool()
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val last = Bool
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}
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case class DataCacheMemRsp(p : DataCacheConfig) extends Bundle{
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val aggregated = UInt(p.aggregationWidth bits)
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val last = Bool()
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val data = Bits(p.memDataWidth bit)
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val error = Bool
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val exclusive = p.withExclusive generate Bool()
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}
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case class DataCacheInv(p : DataCacheConfig) extends Bundle{
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val enable = Bool()
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val address = UInt(p.addressWidth bit)
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}
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case class DataCacheAck(p : DataCacheConfig) extends Bundle{
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val hit = Bool()
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}
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case class DataCacheSync(p : DataCacheConfig) extends Bundle{
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val aggregated = UInt(p.aggregationWidth bits)
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}
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case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave{
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val cmd = Stream (DataCacheMemCmd(p))
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val rsp = Flow (DataCacheMemRsp(p))
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val inv = p.withInvalidate generate Stream(Fragment(DataCacheInv(p)))
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val ack = p.withInvalidate generate Stream(Fragment(DataCacheAck(p)))
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val sync = p.withInvalidate generate Stream(DataCacheSync(p))
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override def asMaster(): Unit = {
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master(cmd)
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slave(rsp)
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if(p.withInvalidate) {
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slave(inv)
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master(ack)
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slave(sync)
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}
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}
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}
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```
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If you don't use memory coherency you can ignore the inv/ack/sync streams, also write cmd should not generate any rsp transaction.
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As the cache is write through, there is no write burst but only individual write transactions.
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The address is in byte and aligned to the bytePerLine config, the size will is encoded as log2(number of bytes in the burst).
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last should be set only on the last transaction of a burst.
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Note that the cmd stream transaction need to be consumed before starting to send back some rsp transactions (1 cycle minimal latency)
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Some documentation about Stream here :
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https://spinalhdl.github.io/SpinalDoc-RTD/master/SpinalHDL/Libraries/stream.html?highlight=stream
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Flow are the same as Stream but without ready signal.
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#### MulPlugin
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#### MulPlugin
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Implements the multiplication instruction from the RISC-V M extension. Its implementation was done in a FPGA friendly way by using 4 17*17 bit multiplications.
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Implements the multiplication instruction from the RISC-V M extension. Its implementation was done in a FPGA friendly way by using 4 17*17 bit multiplications.
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