Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Update Synthesis bench 

Update some synthesis results
This commit is contained in:
Dolu1990 2017-11-17 20:10:46 +01:00
parent 635417aec2
commit 7c19288648
2 changed files with 9 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
README.md
View File

@ -49,7 +49,7 @@ The used CPU corresponding configuration can be find in src/scala/vexriscv/demo.
``` ```
VexRiscv smallest (RV32I, 0.47 DMIPS/Mhz, no datapath bypass, no interrupt) -> VexRiscv smallest (RV32I, 0.47 DMIPS/Mhz, no datapath bypass, no interrupt) ->
Artix 7 -> 372 Mhz 568 LUT 603 FF Artix 7 -> 346 Mhz 481 LUT 539 FF
Cyclone V -> 201 Mhz 347 ALMs Cyclone V -> 201 Mhz 347 ALMs
Cyclone IV -> 190 Mhz 673 LUT 529 FF Cyclone IV -> 190 Mhz 673 LUT 529 FF
Cyclone II -> 154 Mhz 673 LUT 528 FF Cyclone II -> 154 Mhz 673 LUT 528 FF

30
src/main/scala/vexriscv/demo/SynthesisBench.scala
View File

@ -49,7 +49,6 @@ object VexRiscvSynthesisBench {
val targets = XilinxStdTargets( val targets = XilinxStdTargets(
vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin" vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin"
) ++ AlteraStdTargets( ) ++ AlteraStdTargets(
quartusCycloneIIPath = null,
quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin", quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin",
quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin" quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin"
) )
@ -72,28 +71,16 @@ object BrieySynthesisBench {
} }
val rtls = List(briey) val rtls = List(briey)
// val targets = XilinxStdTargets(
// vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin"
// ) ++ AlteraStdTargets(
// quartusCycloneIIPath = null,
// quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin",
// quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin"
// )
//
// Bench(rtls, targets, "/eda/tmp/")
val targets = XilinxStdTargets( val targets = XilinxStdTargets(
vivadoArtix7Path = "E:\\Xilinx\\Vivado\\2016.3\\bin" vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin"
) ++ AlteraStdTargets( ) ++ AlteraStdTargets(
quartusCycloneIIPath = "D:/altera/13.0sp1/quartus/bin64", quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin/",
quartusCycloneIVPath = "D:/altera_lite/15.1/quartus/bin64", quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin/"
quartusCycloneVPath = "D:/altera_lite/15.1/quartus/bin64"
) )
Bench(rtls, targets, "E:/tmp/") Bench(rtls, targets, "/eda/tmp/")
} }
} }
@ -126,13 +113,12 @@ object MuraxSynthesisBench {
val rtls = List(murax, muraxFast) val rtls = List(murax, muraxFast)
val targets = XilinxStdTargets( val targets = XilinxStdTargets(
vivadoArtix7Path = "E:\\Xilinx\\Vivado\\2016.3\\bin" vivadoArtix7Path = "/eda/Xilinx/Vivado/2017.2/bin"
) ++ AlteraStdTargets( ) ++ AlteraStdTargets(
quartusCycloneIIPath = "D:/altera/13.0sp1/quartus/bin64", quartusCycloneIVPath = "/eda/intelFPGA_lite/17.0/quartus/bin/",
quartusCycloneIVPath = "D:/altera_lite/15.1/quartus/bin64", quartusCycloneVPath = "/eda/intelFPGA_lite/17.0/quartus/bin/"
quartusCycloneVPath = "D:/altera_lite/15.1/quartus/bin64"
) )
Bench(rtls, targets, "E:/tmp/") Bench(rtls, targets, "/eda/tmp/")
} }
} }