Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

with no bus stall, pass all tests except uniqueness

This commit is contained in:
Dolu1990 2017-11-06 20:26:45 +01:00
parent e2a432eb5e
commit 8098a03a9b
1 changed files with 7 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
src/main/scala/vexriscv/demo/FormalSimple.scala
View File

@ -38,7 +38,7 @@ object FormalSimple extends App{
separatedAddSub = false, separatedAddSub = false,
executeInsertion = false executeInsertion = false
), ),
new LightShifterPlugin, new FullBarrielShifterPlugin,
new HazardSimplePlugin( new HazardSimplePlugin(
bypassExecute = false, bypassExecute = false,
bypassMemory = false, bypassMemory = false,
@ -57,5 +57,10 @@ object FormalSimple extends App{
) )
) )
) )
SpinalConfig(defaultConfigForClockDomains = ClockDomainConfig(resetKind = spinal.core.SYNC)).generateVerilog(cpu()) SpinalConfig(
defaultConfigForClockDomains = ClockDomainConfig(
resetKind = spinal.core.SYNC,
resetActiveLevel = spinal.core.HIGH
)
).generateVerilog(cpu())
} }