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VexRiscv
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Faster pipeline arbitration logic (200 Mhz on cyclone IV c6) 

Branch plugin with jump in execute or memory stages (parameter)
This commit is contained in:
Charles Papon 2017-03-15 20:02:56 +01:00
parent c6610ea454
commit 83232e9860
2 changed files with 17 additions and 11 deletions
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5
src/main/scala/SpinalRiscv/Pipeline.scala
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@ -108,15 +108,12 @@ trait Pipeline {
val stageBefore = stages(stageIndex - 1) val stageBefore = stages(stageIndex - 1)
val stage = stages(stageIndex) val stage = stages(stageIndex)
when(!stage.arbitration.isStuck) { when(!stage.arbitration.isStuck || stage.arbitration.removeIt) {
stage.arbitration.isValid := False stage.arbitration.isValid := False
} }
when(!stageBefore.arbitration.isStuck && !stageBefore.arbitration.removeIt) { when(!stageBefore.arbitration.isStuck && !stageBefore.arbitration.removeIt) {
stage.arbitration.isValid := stageBefore.arbitration.isValid stage.arbitration.isValid := stageBefore.arbitration.isValid
} }
when(stage.arbitration.removeIt){
stage.arbitration.isValid := False
}
} }
} }

23
src/main/scala/SpinalRiscv/TopLevel.scala
View File

@ -257,6 +257,7 @@ class DecoderSimplePlugin extends Plugin[VexRiscv] with DecoderService {
offset = 0 offset = 0
stageables.foreach(e => { stageables.foreach(e => {
insert(e).assignFromBits(decodedBits(offset, e.dataType.getBitsWidth bits)) insert(e).assignFromBits(decodedBits(offset, e.dataType.getBitsWidth bits))
// insert(e).assignFromBits(RegNext(decodedBits(offset, e.dataType.getBitsWidth bits)))
offset += e.dataType.getBitsWidth offset += e.dataType.getBitsWidth
}) })
} }
@ -273,13 +274,14 @@ class DecoderSimplePlugin extends Plugin[VexRiscv] with DecoderService {
} }
} }
class NoPredictionBranchPlugin extends Plugin[VexRiscv]{ class NoPredictionBranchPlugin(earlyBranch : Boolean) extends Plugin[VexRiscv]{
object BranchCtrlEnum extends SpinalEnum(binarySequential){ object BranchCtrlEnum extends SpinalEnum(binarySequential){
val INC,B,JAL,JALR = newElement() val INC,B,JAL,JALR = newElement()
} }
object BRANCH_CTRL extends Stageable(BranchCtrlEnum()) object BRANCH_CTRL extends Stageable(BranchCtrlEnum())
object BRANCH_SOLVED extends Stageable(BranchCtrlEnum()) object BRANCH_SOLVED extends Stageable(BranchCtrlEnum())
object BRANCH_CALC extends Stageable(UInt(32 bits))
var jumpInterface : Flow[UInt] = null var jumpInterface : Flow[UInt] = null
@ -345,17 +347,24 @@ class NoPredictionBranchPlugin extends Plugin[VexRiscv]{
) )
val imm = IMM(input(INSTRUCTION)) val imm = IMM(input(INSTRUCTION))
jumpInterface.valid := arbitration.isFiring && input(BRANCH_SOLVED) =/= BranchCtrlEnum.INC insert(BRANCH_CALC) := input(BRANCH_SOLVED).mux(
jumpInterface.payload := input(BRANCH_SOLVED).mux(
BranchCtrlEnum.JAL -> (input(PC) + imm.j_sext.asUInt), BranchCtrlEnum.JAL -> (input(PC) + imm.j_sext.asUInt),
BranchCtrlEnum.JALR -> (input(REG1).asUInt + imm.i_sext.asUInt), BranchCtrlEnum.JALR -> (input(REG1).asUInt + imm.i_sext.asUInt),
default -> (input(PC) + imm.b_sext.asUInt) //B default -> (input(PC) + imm.b_sext.asUInt) //B
) )
}
when(jumpInterface.valid){ val branchStage = if(earlyBranch) execute else memory
branchStage plug new Area {
import branchStage._
jumpInterface.valid := arbitration.isFiring && input(BRANCH_SOLVED) =/= BranchCtrlEnum.INC
jumpInterface.payload := input(BRANCH_CALC)
when(jumpInterface.valid) {
prefetch.arbitration.removeIt := True prefetch.arbitration.removeIt := True
fetch.arbitration.removeIt := True fetch.arbitration.removeIt := True
decode.arbitration.removeIt := True decode.arbitration.removeIt := True
if(!earlyBranch) execute.arbitration.removeIt := True
} }
} }
} }
@ -940,7 +949,7 @@ object TopLevel {
new DBusSimplePlugin, new DBusSimplePlugin,
// new HazardSimplePlugin(true,true,true,true), // new HazardSimplePlugin(true,true,true,true),
new HazardSimplePlugin(false, false, false, false), new HazardSimplePlugin(false, false, false, false),
new NoPredictionBranchPlugin new NoPredictionBranchPlugin(false)
) )
val toplevel = new VexRiscv(config) val toplevel = new VexRiscv(config)