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clean some AMO stuff

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This commit is contained in:
Dolu1990 2020-04-08 18:48:01 +02:00
parent 6922f80a87
commit 861df664cf
2 changed files with 5 additions and 4 deletions
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7
src/main/scala/vexriscv/ip/DataCache.scala
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@ -629,6 +629,7 @@ class DataCache(p : DataCacheConfig) extends Component{
if(withExternalLrSc) io.mem.cmd.exclusive := request.isLrsc || (if(withAmo) request.isAmo else False) if(withExternalLrSc) io.mem.cmd.exclusive := request.isLrsc || (if(withAmo) request.isAmo else False)
val bypassCache = mmuRsp.isIoAccess || (if(withExternalLrSc) request.isLrsc else False) val bypassCache = mmuRsp.isIoAccess || (if(withExternalLrSc) request.isLrsc else False)
val isAmoCached = if(withInternalAmo) isAmo else False
when(io.cpu.writeBack.isValid) { when(io.cpu.writeBack.isValid) {
when(bypassCache) { when(bypassCache) {
@ -646,7 +647,7 @@ class DataCache(p : DataCacheConfig) extends Component{
io.cpu.writeBack.haltIt := False io.cpu.writeBack.haltIt := False
} }
} otherwise { } otherwise {
when(waysHit || request.wr && !isAmo) { //Do not require a cache refill ? when(waysHit || request.wr && !isAmoCached) { //Do not require a cache refill ?
cpuWriteToCache := True cpuWriteToCache := True
//Write through //Write through
@ -655,7 +656,7 @@ class DataCache(p : DataCacheConfig) extends Component{
io.mem.cmd.length := 0 io.mem.cmd.length := 0
io.cpu.writeBack.haltIt clearWhen(!request.wr || io.mem.cmd.ready) io.cpu.writeBack.haltIt clearWhen(!request.wr || io.mem.cmd.ready)
if(withAmo) when(isAmo){ if(withInternalAmo) when(isAmo){
when(!internalAmo.resultRegValid) { when(!internalAmo.resultRegValid) {
io.mem.cmd.valid := False io.mem.cmd.valid := False
dataWriteCmd.valid := False dataWriteCmd.valid := False
@ -664,7 +665,7 @@ class DataCache(p : DataCacheConfig) extends Component{
} }
//On write to read dataColisions //On write to read dataColisions
when((!request.wr || isAmo) && (dataColisions & waysHits) =/= 0){ when((!request.wr || isAmoCached) && (dataColisions & waysHits) =/= 0){
io.cpu.redo := True io.cpu.redo := True
if(withAmo) io.mem.cmd.valid := False if(withAmo) io.mem.cmd.valid := False
} }

2
src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
View file

@ -213,7 +213,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
val ff = input(INSTRUCTION)(31 downto 20).as(FenceFlags()) val ff = input(INSTRUCTION)(31 downto 20).as(FenceFlags())
if(withWriteResponse){ if(withWriteResponse){
hazard setWhen(input(MEMORY_FENCE) && (ff.PS && ff.SL)) //Manage write to read hit ordering (ensure invalidation timings) hazard setWhen(input(MEMORY_FENCE) && (ff.PS && ff.SL)) //Manage write to read hit ordering (ensure invalidation timings)
// Not required as LR SC AMO naturaly enforce ordering // Not required as LR SC AMO emited on the memory bus enforce the ordering, + it bypass the cache
// when(input(INSTRUCTION)(26 downto 25) =/= 0){ // when(input(INSTRUCTION)(26 downto 25) =/= 0){
// if(withLrSc) hazard setWhen(input(MEMORY_LRSC)) // if(withLrSc) hazard setWhen(input(MEMORY_LRSC))
// if(withAmo) hazard setWhen(input(MEMORY_AMO)) // if(withAmo) hazard setWhen(input(MEMORY_AMO))