Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix Dynamicfetch/!rvc config

This commit is contained in:
Dolu1990 2018-06-05 02:33:18 +02:00
parent 930563291c
commit 8729530a8d
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/main/scala/vexriscv/plugin/Fetcher.scala
View File

@ -487,7 +487,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean,
val historyWrite = history.writePort val historyWrite = history.writePort
val line = history.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.inputPipeline(0).ready || flush) val line = history.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.inputPipeline(0).ready || flush)
val hit = line.source === (iBusRsp.inputPipeline(0).payload.asBits >> 2 + historyRamSizeLog2) && !(!line.unaligned && iBusRsp.inputPipeline(0).payload(1)) val hit = line.source === (iBusRsp.inputPipeline(0).payload.asBits >> 2 + historyRamSizeLog2) && (if(compressedGen)(!(!line.unaligned && iBusRsp.inputPipeline(0).payload(1))) else True)
//Avoid stoping instruction fetch in the middle patch //Avoid stoping instruction fetch in the middle patch
if(compressedGen && cmdToRspStageCount == 1){ if(compressedGen && cmdToRspStageCount == 1){