Add PMP to golden model
This commit is contained in:
Samuel Lindemer
parent
d5b1a8f565
commit
872aa19d83
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@ -15,156 +15,157 @@ Disassembly of section .crt_section:
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80000014: 30200073 mret
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80000014: 30200073 mret
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80000018 <to_user>:
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80000018 <to_user>:
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80000018: 00014337 lui t1,0x14
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80000018: 00014137 lui sp,0x14
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8000001c: 30033073 csrc mstatus,t1
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8000001c: 30013073 csrc mstatus,sp
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80000020: 20000313 li t1,512
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80000020: 20000113 li sp,512
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80000024: 30032073 csrs mstatus,t1
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80000024: 30012073 csrs mstatus,sp
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80000028: 34109073 csrw mepc,ra
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80000028: 341e9073 csrw mepc,t4
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8000002c: 30200073 mret
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8000002c: 30200073 mret
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80000030 <test0>:
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80000030 <test0>:
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80000030: 00000e13 li t3,0
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80000030: 00000e13 li t3,0
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80000034: 00000f17 auipc t5,0x0
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80000034: 00000f17 auipc t5,0x0
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80000038: 1f0f0f13 addi t5,t5,496 # 80000224 <fail>
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80000038: 1f4f0f13 addi t5,t5,500 # 80000228 <fail>
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8000003c: 800002b7 lui t0,0x80000
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8000003c: 800000b7 lui ra,0x80000
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80000040: 80008e37 lui t3,0x80008
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80000040: 80008237 lui tp,0x80008
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80000044: deadc337 lui t1,0xdeadc
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80000044: deadc137 lui sp,0xdeadc
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80000048: eef30313 addi t1,t1,-273 # deadbeef <pass+0x5eadbcbf>
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80000048: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbcbb>
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8000004c: 0062a023 sw t1,0(t0) # 80000000 <pass+0xfffffdd0>
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8000004c: 0020a023 sw sp,0(ra) # 80000000 <pass+0xfffffdcc>
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80000050: 006e2023 sw t1,0(t3) # 80008000 <pass+0x7dd0>
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80000050: 00222023 sw sp,0(tp) # 80008000 <pass+0x7dcc>
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80000054: 0002a383 lw t2,0(t0)
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80000054: 0000a183 lw gp,0(ra)
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80000058: 1c731663 bne t1,t2,80000224 <fail>
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80000058: 1c311863 bne sp,gp,80000228 <fail>
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8000005c: 000e2383 lw t2,0(t3)
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8000005c: 00022183 lw gp,0(tp) # 0 <_start-0x80000000>
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80000060: 1c731263 bne t1,t2,80000224 <fail>
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80000060: 1c311463 bne sp,gp,80000228 <fail>
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80000064: 071a1f37 lui t5,0x71a1
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80000064: 071a12b7 lui t0,0x71a1
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80000068: 808f0f13 addi t5,t5,-2040 # 71a0808 <_start-0x78e5f7f8>
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80000068: 80828293 addi t0,t0,-2040 # 71a0808 <_start-0x78e5f7f8>
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8000006c: 3a0f1073 csrw pmpcfg0,t5
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8000006c: 3a029073 csrw pmpcfg0,t0
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80000070: 191c0f37 lui t5,0x191c0
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80000070: 191c02b7 lui t0,0x191c0
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80000074: 504f0f13 addi t5,t5,1284 # 191c0504 <_start-0x66e3fafc>
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80000074: 50428293 addi t0,t0,1284 # 191c0504 <_start-0x66e3fafc>
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80000078: 3a1f1073 csrw pmpcfg1,t5
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80000078: 3a129073 csrw pmpcfg1,t0
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8000007c: 01800f13 li t5,24
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8000007c: 01800293 li t0,24
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80000080: 3a2f1073 csrw pmpcfg2,t5
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80000080: 3a229073 csrw pmpcfg2,t0
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80000084: 0f1e2f37 lui t5,0xf1e2
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80000084: 0f1e22b7 lui t0,0xf1e2
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80000088: 900f0f13 addi t5,t5,-1792 # f1e1900 <_start-0x70e1e700>
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80000088: 90028293 addi t0,t0,-1792 # f1e1900 <_start-0x70e1e700>
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8000008c: 3a3f1073 csrw pmpcfg3,t5
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8000008c: 3a329073 csrw pmpcfg3,t0
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80000090: 20000f37 lui t5,0x20000
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80000090: 200002b7 lui t0,0x20000
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80000094: 3b0f1073 csrw pmpaddr0,t5
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80000094: 3b029073 csrw pmpaddr0,t0
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80000098: fff00f13 li t5,-1
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80000098: fff00293 li t0,-1
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8000009c: 3b1f1073 csrw pmpaddr1,t5
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8000009c: 3b129073 csrw pmpaddr1,t0
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800000a0: 20002f37 lui t5,0x20002
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800000a0: 200022b7 lui t0,0x20002
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800000a4: 3b2f1073 csrw pmpaddr2,t5
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800000a4: 3b229073 csrw pmpaddr2,t0
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800000a8: 20004f37 lui t5,0x20004
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800000a8: 200042b7 lui t0,0x20004
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800000ac: ffff0f13 addi t5,t5,-1 # 20003fff <_start-0x5fffc001>
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800000ac: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001>
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800000b0: 3b3f1073 csrw pmpaddr3,t5
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800000b0: 3b329073 csrw pmpaddr3,t0
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800000b4: 20004f37 lui t5,0x20004
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800000b4: 200042b7 lui t0,0x20004
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800000b8: ffff0f13 addi t5,t5,-1 # 20003fff <_start-0x5fffc001>
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800000b8: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001>
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800000bc: 3b4f1073 csrw pmpaddr4,t5
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800000bc: 3b429073 csrw pmpaddr4,t0
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800000c0: 20004f37 lui t5,0x20004
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800000c0: 200042b7 lui t0,0x20004
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800000c4: ffff0f13 addi t5,t5,-1 # 20003fff <_start-0x5fffc001>
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800000c4: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001>
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800000c8: 3b5f1073 csrw pmpaddr5,t5
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800000c8: 3b529073 csrw pmpaddr5,t0
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800000cc: 20002f37 lui t5,0x20002
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800000cc: 200022b7 lui t0,0x20002
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800000d0: ffff0f13 addi t5,t5,-1 # 20001fff <_start-0x5fffe001>
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800000d0: fff28293 addi t0,t0,-1 # 20001fff <_start-0x5fffe001>
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800000d4: 3b6f1073 csrw pmpaddr6,t5
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800000d4: 3b629073 csrw pmpaddr6,t0
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800000d8: 20004f37 lui t5,0x20004
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800000d8: 200042b7 lui t0,0x20004
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800000dc: ffff0f13 addi t5,t5,-1 # 20003fff <_start-0x5fffc001>
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800000dc: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001>
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800000e0: 3b7f1073 csrw pmpaddr7,t5
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800000e0: 3b729073 csrw pmpaddr7,t0
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800000e4: 20004f37 lui t5,0x20004
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800000e4: 200042b7 lui t0,0x20004
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800000e8: ffff0f13 addi t5,t5,-1 # 20003fff <_start-0x5fffc001>
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800000e8: fff28293 addi t0,t0,-1 # 20003fff <_start-0x5fffc001>
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800000ec: 3b8f1073 csrw pmpaddr8,t5
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800000ec: 3b829073 csrw pmpaddr8,t0
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800000f0: 00000f13 li t5,0
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800000f0: 00000293 li t0,0
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800000f4: 3b9f1073 csrw pmpaddr9,t5
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800000f4: 3b929073 csrw pmpaddr9,t0
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800000f8: 00000f13 li t5,0
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800000f8: 00000293 li t0,0
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800000fc: 3baf1073 csrw pmpaddr10,t5
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800000fc: 3ba29073 csrw pmpaddr10,t0
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80000100: 00000f13 li t5,0
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80000100: 00000293 li t0,0
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80000104: 3bbf1073 csrw pmpaddr11,t5
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80000104: 3bb29073 csrw pmpaddr11,t0
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80000108: 00000f13 li t5,0
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80000108: 00000293 li t0,0
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8000010c: 3bcf1073 csrw pmpaddr12,t5
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8000010c: 3bc29073 csrw pmpaddr12,t0
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80000110: 00000f13 li t5,0
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80000110: 00000293 li t0,0
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80000114: 3bdf1073 csrw pmpaddr13,t5
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80000114: 3bd29073 csrw pmpaddr13,t0
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80000118: 00000f13 li t5,0
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80000118: 00000293 li t0,0
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8000011c: 3bef1073 csrw pmpaddr14,t5
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8000011c: 3be29073 csrw pmpaddr14,t0
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80000120: 00000f13 li t5,0
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80000120: 00000293 li t0,0
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80000124: 3bff1073 csrw pmpaddr15,t5
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80000124: 3bf29073 csrw pmpaddr15,t0
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80000128: 00c10337 lui t1,0xc10
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80000128: 00c10137 lui sp,0xc10
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8000012c: fee30313 addi t1,t1,-18 # c0ffee <_start-0x7f3f0012>
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8000012c: fee10113 addi sp,sp,-18 # c0ffee <_start-0x7f3f0012>
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80000130: 0062a023 sw t1,0(t0)
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80000130: 0020a023 sw sp,0(ra)
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80000134: 006e2023 sw t1,0(t3)
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80000134: 00222023 sw sp,0(tp) # 0 <_start-0x80000000>
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80000138: 0002a383 lw t2,0(t0)
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80000138: 0000a183 lw gp,0(ra)
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8000013c: 0e731463 bne t1,t2,80000224 <fail>
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8000013c: 0e311663 bne sp,gp,80000228 <fail>
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80000140: 000e2383 lw t2,0(t3)
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80000140: 00022183 lw gp,0(tp) # 0 <_start-0x80000000>
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80000144: 0e731063 bne t1,t2,80000224 <fail>
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80000144: 0e311263 bne sp,gp,80000228 <fail>
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80000148: 06c0006f j 800001b4 <test3>
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80000148 <test1>:
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8000014c <test1>:
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80000148: 00100e13 li t3,1
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8000014c: 00100e13 li t3,1
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8000014c: 00000f17 auipc t5,0x0
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80000150: 00000f17 auipc t5,0x0
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80000150: 0d8f0f13 addi t5,t5,216 # 80000224 <fail>
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80000154: 0d8f0f13 addi t5,t5,216 # 80000228 <fail>
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80000154: 079a1f37 lui t5,0x79a1
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80000158: 079a12b7 lui t0,0x79a1
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80000158: 808f0f13 addi t5,t5,-2040 # 79a0808 <_start-0x7865f7f8>
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8000015c: 80828293 addi t0,t0,-2040 # 79a0808 <_start-0x7865f7f8>
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8000015c: 3a0f1073 csrw pmpcfg0,t5
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80000160: 3a029073 csrw pmpcfg0,t0
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80000160: deadc337 lui t1,0xdeadc
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80000164: deadc137 lui sp,0xdeadc
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80000164: eef30313 addi t1,t1,-273 # deadbeef <pass+0x5eadbcbf>
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80000168: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbcbb>
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80000168: 006e2023 sw t1,0(t3)
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8000016c: 00222023 sw sp,0(tp) # 0 <_start-0x80000000>
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8000016c: 00000f17 auipc t5,0x0
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80000170: 00000f17 auipc t5,0x0
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80000170: 010f0f13 addi t5,t5,16 # 8000017c <test2>
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80000174: 010f0f13 addi t5,t5,16 # 80000180 <test2>
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80000174: 000e2383 lw t2,0(t3)
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80000178: 00022183 lw gp,0(tp) # 0 <_start-0x80000000>
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80000178: 0ac0006f j 80000224 <fail>
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8000017c: 0ac0006f j 80000228 <fail>
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8000017c <test2>:
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80000180 <test2>:
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8000017c: 00200e13 li t3,2
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80000180: 00200e13 li t3,2
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80000180: 00000f17 auipc t5,0x0
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80000184: 00000f17 auipc t5,0x0
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80000184: 0a4f0f13 addi t5,t5,164 # 80000224 <fail>
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80000188: 0a4f0f13 addi t5,t5,164 # 80000228 <fail>
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80000188: 071a1f37 lui t5,0x71a1
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8000018c: 071a12b7 lui t0,0x71a1
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8000018c: 808f0f13 addi t5,t5,-2040 # 71a0808 <_start-0x78e5f7f8>
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80000190: 80828293 addi t0,t0,-2040 # 71a0808 <_start-0x78e5f7f8>
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80000190: 3a0f1073 csrw pmpcfg0,t5
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80000194: 3a029073 csrw pmpcfg0,t0
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80000194: deadc337 lui t1,0xdeadc
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80000198: deadc137 lui sp,0xdeadc
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80000198: eef30313 addi t1,t1,-273 # deadbeef <pass+0x5eadbcbf>
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8000019c: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbcbb>
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8000019c: 006e2023 sw t1,0(t3)
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800001a0: 00222023 sw sp,0(tp) # 0 <_start-0x80000000>
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800001a0: 00000f17 auipc t5,0x0
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800001a4: 00000f17 auipc t5,0x0
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800001a4: 010f0f13 addi t5,t5,16 # 800001b0 <test3>
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800001a8: 010f0f13 addi t5,t5,16 # 800001b4 <test3>
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800001a8: 000e2383 lw t2,0(t3)
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800001ac: 00022183 lw gp,0(tp) # 0 <_start-0x80000000>
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800001ac: 0780006f j 80000224 <fail>
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800001b0: 0780006f j 80000228 <fail>
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800001b0 <test3>:
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800001b4 <test3>:
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800001b0: 00300e13 li t3,3
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800001b4: 00300e13 li t3,3
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800001b4: 00000f17 auipc t5,0x0
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800001b8: 00000f17 auipc t5,0x0
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800001b8: 070f0f13 addi t5,t5,112 # 80000224 <fail>
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800001bc: 070f0f13 addi t5,t5,112 # 80000228 <fail>
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800001bc: 00000097 auipc ra,0x0
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800001c0: 00000e97 auipc t4,0x0
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800001c0: 00c08093 addi ra,ra,12 # 800001c8 <test4>
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800001c4: 00ce8e93 addi t4,t4,12 # 800001cc <test4>
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800001c4: e55ff06f j 80000018 <to_user>
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800001c8: e51ff06f j 80000018 <to_user>
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800001c8 <test4>:
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800001cc <test4>:
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800001c8: 00400e13 li t3,4
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800001cc: 00400e13 li t3,4
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800001cc: 00000f17 auipc t5,0x0
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800001d0: 00000f17 auipc t5,0x0
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800001d0: 058f0f13 addi t5,t5,88 # 80000224 <fail>
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800001d4: 058f0f13 addi t5,t5,88 # 80000228 <fail>
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800001d4: deadc337 lui t1,0xdeadc
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800001d8: deadc137 lui sp,0xdeadc
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800001d8: eef30313 addi t1,t1,-273 # deadbeef <pass+0x5eadbcbf>
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800001dc: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbcbb>
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800001dc: 006e2023 sw t1,0(t3)
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800001e0: 00222023 sw sp,0(tp) # 0 <_start-0x80000000>
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800001e0: 00000f17 auipc t5,0x0
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800001e4: 00000f17 auipc t5,0x0
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800001e4: 010f0f13 addi t5,t5,16 # 800001f0 <test5>
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800001e8: 010f0f13 addi t5,t5,16 # 800001f4 <test5>
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800001e8: 000e2383 lw t2,0(t3)
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800001ec: 00022183 lw gp,0(tp) # 0 <_start-0x80000000>
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800001ec: 0380006f j 80000224 <fail>
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800001f0: 0380006f j 80000228 <fail>
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800001f0 <test5>:
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800001f4 <test5>:
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800001f0: 00500e13 li t3,5
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800001f4: 00500e13 li t3,5
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800001f4: 00000f17 auipc t5,0x0
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800001f8: 00000f17 auipc t5,0x0
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800001f8: 03cf0f13 addi t5,t5,60 # 80000230 <pass>
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800001fc: 03cf0f13 addi t5,t5,60 # 80000234 <pass>
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800001fc: 80010e37 lui t3,0x80010
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80000200: 80010237 lui tp,0x80010
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80000200: deadc337 lui t1,0xdeadc
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80000204: deadc137 lui sp,0xdeadc
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80000204: eef30313 addi t1,t1,-273 # deadbeef <pass+0x5eadbcbf>
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80000208: eef10113 addi sp,sp,-273 # deadbeef <pass+0x5eadbcbb>
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80000208: 0062a023 sw t1,0(t0)
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8000020c: 0020a023 sw sp,0(ra)
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8000020c: 0002a383 lw t2,0(t0)
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80000210: 0000a183 lw gp,0(ra)
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80000210: 00731a63 bne t1,t2,80000224 <fail>
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80000214: 00311a63 bne sp,gp,80000228 <fail>
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80000214: 000e2383 lw t2,0(t3) # 80010000 <pass+0xfdd0>
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80000218: 00022183 lw gp,0(tp) # 80010000 <pass+0xfdcc>
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80000218: 00000f17 auipc t5,0x0
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8000021c: 00000f17 auipc t5,0x0
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8000021c: 018f0f13 addi t5,t5,24 # 80000230 <pass>
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80000220: 018f0f13 addi t5,t5,24 # 80000234 <pass>
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80000220: 007e2023 sw t2,0(t3)
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80000224: 00322023 sw gp,0(tp) # 0 <_start-0x80000000>
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80000224 <fail>:
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80000228 <fail>:
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80000224: f0100137 lui sp,0xf0100
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80000228: f0100137 lui sp,0xf0100
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80000228: f2410113 addi sp,sp,-220 # f00fff24 <pass+0x700ffcf4>
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8000022c: f2410113 addi sp,sp,-220 # f00fff24 <pass+0x700ffcf0>
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8000022c: 01c12023 sw t3,0(sp)
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80000230: 01c12023 sw t3,0(sp)
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80000230 <pass>:
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80000234 <pass>:
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80000230: f0100137 lui sp,0xf0100
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80000234: f0100137 lui sp,0xf0100
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80000234: f2010113 addi sp,sp,-224 # f00fff20 <pass+0x700ffcf0>
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80000238: f2010113 addi sp,sp,-224 # f00fff20 <pass+0x700ffcec>
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80000238: 00012023 sw zero,0(sp)
|
8000023c: 00012023 sw zero,0(sp)
|
||||||
|
|
|
||||||
Binary file not shown.
|
|
@ -1,39 +1,39 @@
|
||||||
:0200000480007A
|
:0200000480007A
|
||||||
:100000009700000093800001739050306F00400211
|
:100000009700000093800001739050306F00400211
|
||||||
:1000100073101F34730020303743010073300330F6
|
:1000100073101F34730020303741010073300130FA
|
||||||
:1000200013030020732003307390103473002030CA
|
:10002000130100207320013073901E3473002030C0
|
||||||
:10003000130E0000170F0000130F0F1FB7020080F0
|
:10003000130E0000170F0000130F4F1FB7000080B2
|
||||||
:10004000378E008037C3ADDE1303F3EE23A06200CA
|
:100040003782008037C1ADDE1301F1EE23A020001E
|
||||||
:1000500023206E0083A302006316731C83230E000B
|
:100050002320220083A100006318311C83210200A9
|
||||||
:100060006312731C371F1A07130F8F8073100F3A18
|
:100060006314311CB7121A07938282807390023A8C
|
||||||
:10007000370F1C19130F4F5073101F3A130F8001C5
|
:10007000B7021C19938242507390123A9302800186
|
||||||
:1000800073102F3A372F1E0F130F0F9073103F3A34
|
:100080007390223AB7221E0F938202907390323AF5
|
||||||
:10009000370F002073100F3B130FF0FF73101F3B3F
|
:10009000B70200207390023B9302F0FF7390123B73
|
||||||
:1000A000372F002073102F3B374F0020130FFFFF17
|
:1000A000B72200207390223BB74200209382F2FFD8
|
||||||
:1000B00073103F3B374F0020130FFFFF73104F3B70
|
:1000B0007390323BB74200209382F2FF7390423B31
|
||||||
:1000C000374F0020130FFFFF73105F3B372F0020C7
|
:1000C000B74200209382F2FF7390523BB722002088
|
||||||
:1000D000130FFFFF73106F3B374F0020130FFFFF0D
|
:1000D0009382F2FF7390623BB74200209382F2FF5B
|
||||||
:1000E00073107F3B374F0020130FFFFF73108F3BC0
|
:1000E0007390723BB74200209382F2FF7390823B81
|
||||||
:1000F000130F000073109F3B130F00007310AF3BF2
|
:1000F000930200007390923B930200007390A23B26
|
||||||
:10010000130F00007310BF3B130F00007310CF3BA1
|
:10010000930200007390B23B930200007390C23BD5
|
||||||
:10011000130F00007310DF3B130F00007310EF3B51
|
:10011000930200007390D23B930200007390E23B85
|
||||||
:10012000130F00007310FF3B3703C1001303E3FEFE
|
:10012000930200007390F23B3701C1001301E1FE1E
|
||||||
:1001300023A0620023206E0083A302006314730EC9
|
:1001300023A020002320220083A100006316310E9B
|
||||||
:1001400083230E006310730E130E1000170F0000B0
|
:10014000832102006312310E6F00C006130E1000EF
|
||||||
:10015000130F8F0D371F9A07130F8F8073100F3AED
|
:10015000170F0000130F8F0DB7129A07938282803A
|
||||||
:1001600037C3ADDE1303F3EE23206E00170F00003C
|
:100160007390023A37C1ADDE1301F1EE2320220075
|
||||||
:10017000130F0F0183230E006F00C00A130E20001F
|
:10017000170F0000130F0F01832102006F00C00A48
|
||||||
:10018000170F0000130F4F0A371F1A07130F8F8026
|
:10018000130E2000170F0000130F4F0AB7121A07A3
|
||||||
:1001900073100F3A37C3ADDE1303F3EE23206E0066
|
:10019000938282807390023A37C1ADDE1301F1EE93
|
||||||
:1001A000170F0000130F0F0183230E006F0080074D
|
:1001A00023202200170F0000130F0F0183210200EC
|
||||||
:1001B000130E3000170F0000130F0F0797000000F9
|
:1001B0006F008007130E3000170F0000130F0F079A
|
||||||
:1001C0009380C0006FF05FE5130E4000170F000032
|
:1001C000970E0000938ECE006FF01FE5130E4000D7
|
||||||
:1001D000130F8F0537C3ADDE1303F3EE23206E003C
|
:1001D000170F0000130F8F0537C1ADDE1301F1EECD
|
||||||
:1001E000170F0000130F0F0183230E006F00800311
|
:1001E00023202200170F0000130F0F0183210200AC
|
||||||
:1001F000130E5000170F0000130FCF03370E0180AE
|
:1001F0006F008003130E5000170F0000130FCF0382
|
||||||
:1002000037C3ADDE1303F3EE23A0620083A3020025
|
:100200003702018037C1ADDE1301F1EE23A02000DB
|
||||||
:10021000631A730083230E00170F0000130F8F0162
|
:1002100083A10000631A310083210200170F000040
|
||||||
:1002200023207E00370110F0130141F22320C10189
|
:10022000130F8F0123203200370110F0130141F228
|
||||||
:0C023000370110F0130101F2232001003F
|
:100230002320C101370110F0130101F22320010036
|
||||||
:040000058000000077
|
:040000058000000077
|
||||||
:00000001FF
|
:00000001FF
|
||||||
|
|
|
||||||
|
|
@ -15,20 +15,20 @@ LOAD /opt/riscv/lib/gcc/riscv64-unknown-elf/10.2.0/../../../../riscv64-unknown-e
|
||||||
END GROUP
|
END GROUP
|
||||||
LOAD /opt/riscv/lib/gcc/riscv64-unknown-elf/10.2.0/libgcc.a
|
LOAD /opt/riscv/lib/gcc/riscv64-unknown-elf/10.2.0/libgcc.a
|
||||||
|
|
||||||
.crt_section 0x0000000080000000 0x23c
|
.crt_section 0x0000000080000000 0x240
|
||||||
0x0000000080000000 . = ALIGN (0x4)
|
0x0000000080000000 . = ALIGN (0x4)
|
||||||
*crt.o(.text)
|
*crt.o(.text)
|
||||||
.text 0x0000000080000000 0x23c build/src/crt.o
|
.text 0x0000000080000000 0x240 build/src/crt.o
|
||||||
0x0000000080000000 _start
|
0x0000000080000000 _start
|
||||||
0x0000000080000010 trap
|
0x0000000080000010 trap
|
||||||
0x0000000080000018 to_user
|
0x0000000080000018 to_user
|
||||||
OUTPUT(build/pmp.elf elf32-littleriscv)
|
OUTPUT(build/pmp.elf elf32-littleriscv)
|
||||||
|
|
||||||
.data 0x000000008000023c 0x0
|
.data 0x0000000080000240 0x0
|
||||||
.data 0x000000008000023c 0x0 build/src/crt.o
|
.data 0x0000000080000240 0x0 build/src/crt.o
|
||||||
|
|
||||||
.bss 0x000000008000023c 0x0
|
.bss 0x0000000080000240 0x0
|
||||||
.bss 0x000000008000023c 0x0 build/src/crt.o
|
.bss 0x0000000080000240 0x0 build/src/crt.o
|
||||||
|
|
||||||
.riscv.attributes
|
.riscv.attributes
|
||||||
0x0000000000000000 0x1e
|
0x0000000000000000 0x1e
|
||||||
|
|
|
||||||
|
|
@ -5,6 +5,7 @@
|
||||||
*/
|
*/
|
||||||
|
|
||||||
#define TEST_ID x28
|
#define TEST_ID x28
|
||||||
|
#define USER_RA x29
|
||||||
#define TRAP_RA x30
|
#define TRAP_RA x30
|
||||||
|
|
||||||
#define PMPCFG0 0x071a0808
|
#define PMPCFG0 0x071a0808
|
||||||
|
|
@ -43,11 +44,11 @@ trap:
|
||||||
|
|
||||||
.global to_user
|
.global to_user
|
||||||
to_user:
|
to_user:
|
||||||
li t1, 0x14000
|
li x2, 0x14000
|
||||||
csrc mstatus, t1
|
csrc mstatus, x2
|
||||||
li t1, 0x200
|
li x2, 0x200
|
||||||
csrs mstatus, t1
|
csrs mstatus, x2
|
||||||
csrw mepc, ra
|
csrw mepc, USER_RA
|
||||||
mret
|
mret
|
||||||
|
|
||||||
// configure PMP, attempt read/write from machine mode
|
// configure PMP, attempt read/write from machine mode
|
||||||
|
|
@ -55,118 +56,118 @@ test0:
|
||||||
li TEST_ID, 0
|
li TEST_ID, 0
|
||||||
la TRAP_RA, fail
|
la TRAP_RA, fail
|
||||||
|
|
||||||
li t0, 0x80000000
|
li x1, 0x80000000
|
||||||
li t3, 0x80008000
|
li x4, 0x80008000
|
||||||
li t1, 0xdeadbeef
|
li x2, 0xdeadbeef
|
||||||
sw t1, 0x0(t0)
|
sw x2, 0x0(x1)
|
||||||
sw t1, 0x0(t3)
|
sw x2, 0x0(x4)
|
||||||
lw t2, 0x0(t0)
|
lw x3, 0x0(x1)
|
||||||
bne t1, t2, fail
|
bne x2, x3, fail
|
||||||
lw t2, 0x0(t3)
|
lw x3, 0x0(x4)
|
||||||
bne t1, t2, fail
|
bne x2, x3, fail
|
||||||
|
|
||||||
li t5, PMPCFG0
|
li x5, PMPCFG0
|
||||||
csrw pmpcfg0, t5
|
csrw pmpcfg0, x5
|
||||||
li t5, PMPCFG1
|
li x5, PMPCFG1
|
||||||
csrw pmpcfg1, t5
|
csrw pmpcfg1, x5
|
||||||
li t5, PMPCFG2
|
li x5, PMPCFG2
|
||||||
csrw pmpcfg2, t5
|
csrw pmpcfg2, x5
|
||||||
li t5, PMPCFG3
|
li x5, PMPCFG3
|
||||||
csrw pmpcfg3, t5
|
csrw pmpcfg3, x5
|
||||||
li t5, PMPADDR0
|
li x5, PMPADDR0
|
||||||
csrw pmpaddr0, t5
|
csrw pmpaddr0, x5
|
||||||
li t5, PMPADDR1
|
li x5, PMPADDR1
|
||||||
csrw pmpaddr1, t5
|
csrw pmpaddr1, x5
|
||||||
li t5, PMPADDR2
|
li x5, PMPADDR2
|
||||||
csrw pmpaddr2, t5
|
csrw pmpaddr2, x5
|
||||||
li t5, PMPADDR3
|
li x5, PMPADDR3
|
||||||
csrw pmpaddr3, t5
|
csrw pmpaddr3, x5
|
||||||
li t5, PMPADDR4
|
li x5, PMPADDR4
|
||||||
csrw pmpaddr4, t5
|
csrw pmpaddr4, x5
|
||||||
li t5, PMPADDR5
|
li x5, PMPADDR5
|
||||||
csrw pmpaddr5, t5
|
csrw pmpaddr5, x5
|
||||||
li t5, PMPADDR6
|
li x5, PMPADDR6
|
||||||
csrw pmpaddr6, t5
|
csrw pmpaddr6, x5
|
||||||
li t5, PMPADDR7
|
li x5, PMPADDR7
|
||||||
csrw pmpaddr7, t5
|
csrw pmpaddr7, x5
|
||||||
li t5, PMPADDR8
|
li x5, PMPADDR8
|
||||||
csrw pmpaddr8, t5
|
csrw pmpaddr8, x5
|
||||||
li t5, PMPADDR9
|
li x5, PMPADDR9
|
||||||
csrw pmpaddr9, t5
|
csrw pmpaddr9, x5
|
||||||
li t5, PMPADDR10
|
li x5, PMPADDR10
|
||||||
csrw pmpaddr10, t5
|
csrw pmpaddr10, x5
|
||||||
li t5, PMPADDR11
|
li x5, PMPADDR11
|
||||||
csrw pmpaddr11, t5
|
csrw pmpaddr11, x5
|
||||||
li t5, PMPADDR12
|
li x5, PMPADDR12
|
||||||
csrw pmpaddr12, t5
|
csrw pmpaddr12, x5
|
||||||
li t5, PMPADDR13
|
li x5, PMPADDR13
|
||||||
csrw pmpaddr13, t5
|
csrw pmpaddr13, x5
|
||||||
li t5, PMPADDR14
|
li x5, PMPADDR14
|
||||||
csrw pmpaddr14, t5
|
csrw pmpaddr14, x5
|
||||||
li t5, PMPADDR15
|
li x5, PMPADDR15
|
||||||
csrw pmpaddr15, t5
|
csrw pmpaddr15, x5
|
||||||
|
|
||||||
li t1, 0x00c0ffee
|
li x2, 0x00c0ffee
|
||||||
sw t1, 0x0(t0)
|
sw x2, 0x0(x1)
|
||||||
sw t1, 0x0(t3)
|
sw x2, 0x0(x4)
|
||||||
lw t2, 0x0(t0)
|
lw x3, 0x0(x1)
|
||||||
bne t1, t2, fail
|
bne x2, x3, fail
|
||||||
lw t2, 0x0(t3)
|
lw x3, 0x0(x4)
|
||||||
bne t1, t2, fail
|
bne x2, x3, fail
|
||||||
|
|
||||||
// lock region 2, attempt read/write from machine mode
|
// lock region 2, attempt read/write from machine mode
|
||||||
test1:
|
test1:
|
||||||
li TEST_ID, 1
|
li TEST_ID, 1
|
||||||
la TRAP_RA, fail
|
la TRAP_RA, fail
|
||||||
li t5, PMPCFG0_
|
li x5, PMPCFG0_
|
||||||
csrw pmpcfg0, t5 // lock region 2
|
csrw pmpcfg0, x5 // lock region 2
|
||||||
li t1, 0xdeadbeef
|
li x2, 0xdeadbeef
|
||||||
sw t1, 0x0(t3) // should be OK (write 0x80008000)
|
sw x2, 0x0(x4) // should be OK (write 0x80008000)
|
||||||
la TRAP_RA, test2
|
la TRAP_RA, test2
|
||||||
lw t2, 0x0(t3) // should fault (read 0x80008000)
|
lw x3, 0x0(x4) // should fault (read 0x80008000)
|
||||||
j fail
|
j fail
|
||||||
|
|
||||||
// "unlock" region 2, attempt read/write from machine mode
|
// "unlock" region 2, attempt read/write from machine mode
|
||||||
test2:
|
test2:
|
||||||
li TEST_ID, 2
|
li TEST_ID, 2
|
||||||
la TRAP_RA, fail
|
la TRAP_RA, fail
|
||||||
li t5, PMPCFG0
|
li x5, PMPCFG0
|
||||||
csrw pmpcfg0, t5 // "unlock" region 2
|
csrw pmpcfg0, x5 // "unlock" region 2
|
||||||
li t1, 0xdeadbeef
|
li x2, 0xdeadbeef
|
||||||
sw t1, 0x0(t3) // should still be OK (write 0x80008000)
|
sw x2, 0x0(x4) // should still be OK (write 0x80008000)
|
||||||
la TRAP_RA, test3
|
la TRAP_RA, test3
|
||||||
lw t2, 0x0(t3) // should still fault (read 0x80008000)
|
lw x3, 0x0(x4) // should still fault (read 0x80008000)
|
||||||
j fail
|
j fail
|
||||||
|
|
||||||
// jump into user mode
|
// jump into user mode
|
||||||
test3:
|
test3:
|
||||||
li TEST_ID, 3
|
li TEST_ID, 3
|
||||||
la TRAP_RA, fail
|
la TRAP_RA, fail
|
||||||
la ra, test4
|
la USER_RA, test4
|
||||||
j to_user
|
j to_user
|
||||||
|
|
||||||
// attempt to read/write region 2 from user mode
|
// attempt to read/write region 2 from user mode
|
||||||
test4:
|
test4:
|
||||||
li TEST_ID, 4
|
li TEST_ID, 4
|
||||||
la TRAP_RA, fail
|
la TRAP_RA, fail
|
||||||
li t1, 0xdeadbeef
|
li x2, 0xdeadbeef
|
||||||
sw t1, 0x0(t3) // should be OK (write 0x80008000)
|
sw x2, 0x0(x4) // should be OK (write 0x80008000)
|
||||||
la TRAP_RA, test5
|
la TRAP_RA, test5
|
||||||
lw t2, 0x0(t3) // should fault (read 0x80008000)
|
lw x3, 0x0(x4) // should fault (read 0x80008000)
|
||||||
j fail
|
j fail
|
||||||
|
|
||||||
// attempt to read/write other regions from user mode
|
// attempt to read/write other regions from user mode
|
||||||
test5:
|
test5:
|
||||||
li TEST_ID, 5
|
li TEST_ID, 5
|
||||||
la TRAP_RA, pass
|
la TRAP_RA, pass
|
||||||
li t3, 0x80010000
|
li x4, 0x80010000
|
||||||
li t1, 0xdeadbeef
|
li x2, 0xdeadbeef
|
||||||
sw t1, 0x0(t0)
|
sw x2, 0x0(x1)
|
||||||
lw t2, 0x0(t0)
|
lw x3, 0x0(x1)
|
||||||
bne t1, t2, fail // should be OK
|
bne x2, x3, fail // should be OK
|
||||||
lw t2, 0x0(t3) // should be OK (read 0x80010000)
|
lw x3, 0x0(x4) // should be OK (read 0x80010000)
|
||||||
la TRAP_RA, pass
|
la TRAP_RA, pass
|
||||||
sw t2, 0x0(t3) // should fault (write 0x80010000)
|
sw x3, 0x0(x4) // should fault (write 0x80010000)
|
||||||
|
|
||||||
fail:
|
fail:
|
||||||
li x2, 0xf00fff24
|
li x2, 0xf00fff24
|
||||||
|
|
|
||||||
|
|
@ -211,6 +211,26 @@ class success : public std::exception { };
|
||||||
#define MCYCLEH 0xB80 // MRW Upper 32 bits of mcycle, RV32I only.
|
#define MCYCLEH 0xB80 // MRW Upper 32 bits of mcycle, RV32I only.
|
||||||
#define MINSTRETH 0xB82 // MRW Upper 32 bits of minstret, RV32I only.
|
#define MINSTRETH 0xB82 // MRW Upper 32 bits of minstret, RV32I only.
|
||||||
|
|
||||||
|
#define PMPCFG0 0x3a0
|
||||||
|
#define PMPCFG1 0x3a1
|
||||||
|
#define PMPCFG2 0x3a2
|
||||||
|
#define PMPCFG3 0x3a3
|
||||||
|
#define PMPADDR0 0x3b0
|
||||||
|
#define PMPADDR1 0x3b1
|
||||||
|
#define PMPADDR2 0x3b2
|
||||||
|
#define PMPADDR3 0x3b3
|
||||||
|
#define PMPADDR4 0x3b4
|
||||||
|
#define PMPADDR5 0x3b5
|
||||||
|
#define PMPADDR6 0x3b6
|
||||||
|
#define PMPADDR7 0x3b7
|
||||||
|
#define PMPADDR8 0x3b8
|
||||||
|
#define PMPADDR9 0x3b9
|
||||||
|
#define PMPADDR10 0x3ba
|
||||||
|
#define PMPADDR11 0x3bb
|
||||||
|
#define PMPADDR12 0x3bc
|
||||||
|
#define PMPADDR13 0x3bd
|
||||||
|
#define PMPADDR14 0x3be
|
||||||
|
#define PMPADDR15 0x3bf
|
||||||
|
|
||||||
#define SSTATUS 0x100
|
#define SSTATUS 0x100
|
||||||
#define SIE 0x104
|
#define SIE 0x104
|
||||||
|
|
@ -373,10 +393,26 @@ public:
|
||||||
uint32_t ppn1 : 12;
|
uint32_t ppn1 : 12;
|
||||||
};
|
};
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
bool lrscReserved;
|
bool lrscReserved;
|
||||||
|
|
||||||
|
struct pmpcfg_s {
|
||||||
|
uint32_t r : 1;
|
||||||
|
uint32_t w : 1;
|
||||||
|
uint32_t x : 1;
|
||||||
|
uint32_t a : 2;
|
||||||
|
uint32_t _dummy : 2;
|
||||||
|
uint32_t l : 1;
|
||||||
|
} __attribute__((packed));
|
||||||
|
|
||||||
|
union pmpcfg_u {
|
||||||
|
uint32_t raw;
|
||||||
|
pmpcfg_s reg[4];
|
||||||
|
};
|
||||||
|
|
||||||
|
pmpcfg_u pmpcfg[4];
|
||||||
|
uint32_t pmpaddr[16];
|
||||||
|
|
||||||
RiscvGolden() {
|
RiscvGolden() {
|
||||||
pc = 0x80000000;
|
pc = 0x80000000;
|
||||||
regs[0] = 0;
|
regs[0] = 0;
|
||||||
|
|
@ -401,6 +437,10 @@ public:
|
||||||
ipInput = 0;
|
ipInput = 0;
|
||||||
stepCounter = 0;
|
stepCounter = 0;
|
||||||
lrscReserved = false;
|
lrscReserved = false;
|
||||||
|
for (int i = 0; i < 4; i++)
|
||||||
|
pmpcfg[i].raw = 0;
|
||||||
|
for (int i = 0; i < 16; i++)
|
||||||
|
pmpaddr[i] = 0;
|
||||||
}
|
}
|
||||||
|
|
||||||
virtual void rfWrite(int32_t address, int32_t data) {
|
virtual void rfWrite(int32_t address, int32_t data) {
|
||||||
|
|
@ -425,8 +465,55 @@ public:
|
||||||
|
|
||||||
enum AccessKind {READ,WRITE,EXECUTE,READ_WRITE};
|
enum AccessKind {READ,WRITE,EXECUTE,READ_WRITE};
|
||||||
virtual bool isMmuRegion(uint32_t v) = 0;
|
virtual bool isMmuRegion(uint32_t v) = 0;
|
||||||
bool v2p(uint32_t v, uint32_t *p, AccessKind kind){
|
|
||||||
uint32_t effectivePrivilege = status.mprv && kind != EXECUTE ? status.mpp : privilege;
|
bool pmpCheck(uint32_t p, AccessKind kind) {
|
||||||
|
for (int i = 0; i < 4; i++) {
|
||||||
|
for (int j = 0; j < 4; j++) {
|
||||||
|
if (privilege != 3 || pmpcfg[i].reg[3-j].l) {
|
||||||
|
uint32_t start, end;
|
||||||
|
bool valid = false;
|
||||||
|
|
||||||
|
switch (pmpcfg[i].reg[3-j].a) {
|
||||||
|
case 0: // OFF
|
||||||
|
valid = false;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 1: // TOR
|
||||||
|
valid = false;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 2: // NA4
|
||||||
|
valid = true;
|
||||||
|
start = pmpaddr[i*4+j] << 2;
|
||||||
|
end = start + 4;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case 3: // NAPOT
|
||||||
|
valid = true;
|
||||||
|
uint32_t mask = pmpaddr[i*4+j] & ~(pmpaddr[i*4+j] + 1);
|
||||||
|
start = (pmpaddr[i*4+j] & ~mask) << 2;
|
||||||
|
end = start + ((mask + 1) << 3);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (valid && start <= p && end > p) {
|
||||||
|
if (kind == READ) return (bool)(!pmpcfg[i].reg[3-j].r);
|
||||||
|
if (kind == WRITE) return (bool)(!pmpcfg[i].reg[3-j].w);
|
||||||
|
if (kind == EXECUTE) return (bool)(!pmpcfg[i].reg[3-j].x);
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return false;
|
||||||
|
}
|
||||||
|
|
||||||
|
bool v2p(uint32_t v, uint32_t *p, AccessKind kind) {
|
||||||
|
#ifdef PMP
|
||||||
|
*p = v;
|
||||||
|
return pmpCheck(v, kind);
|
||||||
|
#else
|
||||||
|
uint32_t effectivePrivilege = status.mprv && kind != EXECUTE ? status.mpp : privilege;
|
||||||
if(effectivePrivilege == 3 || satp.mode == 0 || !isMmuRegion(v)){
|
if(effectivePrivilege == 3 || satp.mode == 0 || !isMmuRegion(v)){
|
||||||
*p = v;
|
*p = v;
|
||||||
} else {
|
} else {
|
||||||
|
|
@ -449,6 +536,7 @@ public:
|
||||||
*p = (tlb.ppn1 << 22) | (superPage ? v & 0x3FF000 : tlb.ppn0 << 12) | (v & 0xFFF);
|
*p = (tlb.ppn1 << 22) | (superPage ? v & 0x3FF000 : tlb.ppn0 << 12) | (v & 0xFFF);
|
||||||
}
|
}
|
||||||
return false;
|
return false;
|
||||||
|
#endif
|
||||||
}
|
}
|
||||||
|
|
||||||
void trap(bool interrupt,int32_t cause) {
|
void trap(bool interrupt,int32_t cause) {
|
||||||
|
|
@ -528,7 +616,7 @@ public:
|
||||||
|
|
||||||
virtual bool csrRead(int32_t csr, uint32_t *value){
|
virtual bool csrRead(int32_t csr, uint32_t *value){
|
||||||
if(((csr >> 8) & 0x3) > privilege) return true;
|
if(((csr >> 8) & 0x3) > privilege) return true;
|
||||||
switch(csr){
|
switch(csr) {
|
||||||
case MSTATUS: *value = status.raw & MSTATUS_READ_MASK; break;
|
case MSTATUS: *value = status.raw & MSTATUS_READ_MASK; break;
|
||||||
case MIP: *value = getIp().raw; break;
|
case MIP: *value = getIp().raw; break;
|
||||||
case MIE: *value = ie.raw; break;
|
case MIE: *value = ie.raw; break;
|
||||||
|
|
@ -550,6 +638,28 @@ public:
|
||||||
case SEPC: *value = sepc; break;
|
case SEPC: *value = sepc; break;
|
||||||
case SSCRATCH: *value = sscratch; break;
|
case SSCRATCH: *value = sscratch; break;
|
||||||
case SATP: *value = satp.raw; break;
|
case SATP: *value = satp.raw; break;
|
||||||
|
|
||||||
|
case PMPCFG0: *value = pmpcfg[0].raw; break;
|
||||||
|
case PMPCFG1: *value = pmpcfg[1].raw; break;
|
||||||
|
case PMPCFG2: *value = pmpcfg[2].raw; break;
|
||||||
|
case PMPCFG3: *value = pmpcfg[3].raw; break;
|
||||||
|
case PMPADDR0: *value = pmpaddr[0]; break;
|
||||||
|
case PMPADDR1: *value = pmpaddr[1]; break;
|
||||||
|
case PMPADDR2: *value = pmpaddr[2]; break;
|
||||||
|
case PMPADDR3: *value = pmpaddr[3]; break;
|
||||||
|
case PMPADDR4: *value = pmpaddr[4]; break;
|
||||||
|
case PMPADDR5: *value = pmpaddr[5]; break;
|
||||||
|
case PMPADDR6: *value = pmpaddr[6]; break;
|
||||||
|
case PMPADDR7: *value = pmpaddr[7]; break;
|
||||||
|
case PMPADDR8: *value = pmpaddr[8]; break;
|
||||||
|
case PMPADDR9: *value = pmpaddr[9]; break;
|
||||||
|
case PMPADDR10: *value = pmpaddr[10]; break;
|
||||||
|
case PMPADDR11: *value = pmpaddr[11]; break;
|
||||||
|
case PMPADDR12: *value = pmpaddr[12]; break;
|
||||||
|
case PMPADDR13: *value = pmpaddr[13]; break;
|
||||||
|
case PMPADDR14: *value = pmpaddr[14]; break;
|
||||||
|
case PMPADDR15: *value = pmpaddr[15]; break;
|
||||||
|
|
||||||
default: return true; break;
|
default: return true; break;
|
||||||
}
|
}
|
||||||
return false;
|
return false;
|
||||||
|
|
@ -591,6 +701,48 @@ public:
|
||||||
case SSCRATCH: sscratch = value; break;
|
case SSCRATCH: sscratch = value; break;
|
||||||
case SATP: satp.raw = value; break;
|
case SATP: satp.raw = value; break;
|
||||||
|
|
||||||
|
case PMPCFG0:
|
||||||
|
if (!pmpcfg[0].reg[3].l) maskedWrite(pmpcfg[0].raw, value, 0xff);
|
||||||
|
if (!pmpcfg[0].reg[2].l) maskedWrite(pmpcfg[0].raw, value, 0xff00);
|
||||||
|
if (!pmpcfg[0].reg[1].l) maskedWrite(pmpcfg[0].raw, value, 0xff0000);
|
||||||
|
if (!pmpcfg[0].reg[0].l) maskedWrite(pmpcfg[0].raw, value, 0xff000000);
|
||||||
|
break;
|
||||||
|
case PMPCFG1:
|
||||||
|
if (!pmpcfg[1].reg[3].l) maskedWrite(pmpcfg[1].raw, value, 0xff);
|
||||||
|
if (!pmpcfg[1].reg[2].l) maskedWrite(pmpcfg[1].raw, value, 0xff00);
|
||||||
|
if (!pmpcfg[1].reg[1].l) maskedWrite(pmpcfg[1].raw, value, 0xff0000);
|
||||||
|
if (!pmpcfg[1].reg[0].l) maskedWrite(pmpcfg[1].raw, value, 0xff000000);
|
||||||
|
break;
|
||||||
|
case PMPCFG2:
|
||||||
|
if (!pmpcfg[2].reg[3].l) maskedWrite(pmpcfg[2].raw, value, 0xff);
|
||||||
|
if (!pmpcfg[2].reg[2].l) maskedWrite(pmpcfg[2].raw, value, 0xff00);
|
||||||
|
if (!pmpcfg[2].reg[1].l) maskedWrite(pmpcfg[2].raw, value, 0xff0000);
|
||||||
|
if (!pmpcfg[2].reg[0].l) maskedWrite(pmpcfg[2].raw, value, 0xff000000);
|
||||||
|
break;
|
||||||
|
case PMPCFG3:
|
||||||
|
if (!pmpcfg[3].reg[3].l) maskedWrite(pmpcfg[3].raw, value, 0xff);
|
||||||
|
if (!pmpcfg[3].reg[2].l) maskedWrite(pmpcfg[3].raw, value, 0xff00);
|
||||||
|
if (!pmpcfg[3].reg[1].l) maskedWrite(pmpcfg[3].raw, value, 0xff0000);
|
||||||
|
if (!pmpcfg[3].reg[0].l) maskedWrite(pmpcfg[3].raw, value, 0xff000000);
|
||||||
|
break;
|
||||||
|
|
||||||
|
case PMPADDR0: pmpaddr[0] = value; break;
|
||||||
|
case PMPADDR1: pmpaddr[1] = value; break;
|
||||||
|
case PMPADDR2: pmpaddr[2] = value; break;
|
||||||
|
case PMPADDR3: pmpaddr[3] = value; break;
|
||||||
|
case PMPADDR4: pmpaddr[4] = value; break;
|
||||||
|
case PMPADDR5: pmpaddr[5] = value; break;
|
||||||
|
case PMPADDR6: pmpaddr[6] = value; break;
|
||||||
|
case PMPADDR7: pmpaddr[7] = value; break;
|
||||||
|
case PMPADDR8: pmpaddr[8] = value; break;
|
||||||
|
case PMPADDR9: pmpaddr[9] = value; break;
|
||||||
|
case PMPADDR10: pmpaddr[10] = value; break;
|
||||||
|
case PMPADDR11: pmpaddr[11] = value; break;
|
||||||
|
case PMPADDR12: pmpaddr[12] = value; break;
|
||||||
|
case PMPADDR13: pmpaddr[13] = value; break;
|
||||||
|
case PMPADDR14: pmpaddr[14] = value; break;
|
||||||
|
case PMPADDR15: pmpaddr[15] = value; break;
|
||||||
|
|
||||||
default: ilegalInstruction(); return true; break;
|
default: ilegalInstruction(); return true; break;
|
||||||
}
|
}
|
||||||
return false;
|
return false;
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue