FpuCore can add/mul/fma/store/load
This commit is contained in:
Dolu1990
parent
6e0be6e18c
commit
8761d0d9ee
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package vexriscv.ip.fpu
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import spinal.core._
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import spinal.lib._
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import spinal.lib.eda.bench.{Bench, Rtl, XilinxStdTargets}
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import scala.collection.mutable.ArrayBuffer
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case class FpuCore(p : FpuParameter) extends Component{
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val io = new Bundle {
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val port = slave(FpuPort(p))
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}
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val rfLockCount = 5
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val lockIdType = HardType(UInt(log2Up(rfLockCount) bits))
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io.port.rsp.valid := False
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io.port.rsp.payload.assignDontCare()
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case class RfReadInput() extends Bundle{
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val source = p.source()
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val opcode = p.Opcode()
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val rs1, rs2, rs3 = p.rfAddress()
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val rd = p.rfAddress()
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}
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case class RfReadOutput() extends Bundle{
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val source = p.source()
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val opcode = p.Opcode()
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val lockId = lockIdType()
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val rs1, rs2, rs3 = p.internalFloating()
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val rd = p.rfAddress()
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}
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case class LoadInput() extends Bundle{
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val source = p.source()
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val rs1 = p.internalFloating()
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val rd = p.rfAddress()
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val lockId = lockIdType()
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}
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case class StoreInput() extends Bundle{
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val source = p.source()
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val rs2 = p.internalFloating()
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}
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case class MulInput() extends Bundle{
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val source = p.source()
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val rs1, rs2, rs3 = p.internalFloating()
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val rd = p.rfAddress()
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val lockId = lockIdType()
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val add = Bool()
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val minus = Bool()
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}
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case class AddInput() extends Bundle{
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val source = p.source()
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val rs1, rs2 = p.internalFloating()
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val rd = p.rfAddress()
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val lockId = lockIdType()
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}
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case class WriteInput() extends Bundle{
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val source = p.source()
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val lockId = lockIdType()
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val rd = p.rfAddress()
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val value = p.internalFloating()
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}
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val rf = new Area{
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val ram = Mem(p.internalFloating, 32*(1 << p.sourceWidth))
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val lock = for(i <- 0 until rfLockCount) yield new Area{
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val valid = RegInit(False)
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val source = Reg(p.source)
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val address = Reg(p.rfAddress)
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}
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val lockFree = !lock.map(_.valid).andR
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val lockFreeId = OHMasking.first(lock.map(!_.valid))
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}
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val read = new Area{
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val s0 = Stream(RfReadInput())
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s0.arbitrationFrom(io.port.cmd)
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s0.payload.assignSomeByName(io.port.cmd.payload)
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val useRs1, useRs2, useRs3, useRd = False
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switch(s0.opcode){
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is(p.Opcode.LOAD){
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useRd := True
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}
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is(p.Opcode.STORE){
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useRs2 := True
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}
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is(p.Opcode.ADD){
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useRs1 := True
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useRs2 := True
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useRd := True
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}
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is(p.Opcode.MUL){
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useRs1 := True
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useRs2 := True
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useRd := True
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}
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is(p.Opcode.FMA){
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useRs1 := True
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useRs2 := True
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useRs3 := True //Can be delayed to have less hazard
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useRd := True
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}
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}
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val hits = List((useRs1, s0.rs1), (useRs2, s0.rs2), (useRs3, s0.rs3), (useRd, s0.rd)).map{case (use, reg) => use && rf.lock.map(l => l.valid && l.source === s0.source && l.address === reg).orR}
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val hazard = hits.orR
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when(s0.fire && useRd){
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for(i <- 0 until rfLockCount){
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when(rf.lockFreeId(i)){
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rf.lock(i).valid := True
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rf.lock(i).source := s0.source
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rf.lock(i).address := s0.rd
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}
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}
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}
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val s1 = s0.haltWhen(hazard || !rf.lockFree).m2sPipe()
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val output = s1.swapPayload(RfReadOutput())
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val s1LockId = RegNextWhen(OHToUInt(rf.lockFreeId), !output.isStall)
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output.source := s1.source
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output.opcode := s1.opcode
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output.lockId := s1LockId
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output.rd := s1.rd
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output.rs1 := rf.ram.readSync(s0.rs1,enable = !output.isStall)
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output.rs2 := rf.ram.readSync(s0.rs2,enable = !output.isStall)
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output.rs3 := rf.ram.readSync(s0.rs3,enable = !output.isStall)
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}
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val decode = new Area{
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val input = read.output.combStage()
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input.ready := False
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val loadHit = input.opcode === p.Opcode.LOAD
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val load = Stream(LoadInput())
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load.valid := input.valid && loadHit
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input.ready setWhen(loadHit && load.ready)
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load.source := read.output.source
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load.rd := read.output.rd
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load.rs1 := read.output.rs1
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load.lockId := read.output.lockId
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val storeHit = input.opcode === p.Opcode.STORE
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val store = Stream(StoreInput())
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input.ready setWhen(storeHit && store.ready)
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store.valid := input.valid && storeHit
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store.source := read.output.source
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store.rs2 := read.output.rs2
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val fmaHit = input.opcode === p.Opcode.FMA
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val mulHit = input.opcode === p.Opcode.MUL || fmaHit
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val mul = Stream(MulInput())
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input.ready setWhen(mulHit && mul.ready)
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mul.valid := input.valid && mulHit
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mul.source := read.output.source
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mul.rs1 := read.output.rs1
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mul.rs2 := read.output.rs2
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mul.rs3 := read.output.rs3
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mul.rd := read.output.rd
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mul.lockId := read.output.lockId
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mul.add := fmaHit
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mul.minus := False //TODO
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val addHit = input.opcode === p.Opcode.ADD
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val add = Stream(AddInput())
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val mulToAdd = Stream(AddInput())
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input.ready setWhen(addHit && add.ready && !mulToAdd.valid)
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add.valid := input.valid && addHit || mulToAdd.valid
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mulToAdd.ready := add.ready
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add.payload := mulToAdd.payload
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when(!mulToAdd.valid) {
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add.payload.assignSomeByName(read.output.payload)
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}
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}
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val load = new Area{
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def input = decode.load
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val output = input.stage()
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}
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val store = new Area{
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val input = decode.store.stage()
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input.ready := io.port.rsp.ready
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when(input.valid){
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io.port.rsp.valid := True
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io.port.rsp.source := input.source
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io.port.rsp.value := input.rs2.asBits
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}
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}
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val mul = new Area{
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val input = decode.mul.stage()
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val math = new Area {
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val mulA = U"1" @@ input.rs1.mantissa
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val mulB = U"1" @@ input.rs2.mantissa
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val mulC = mulA * mulB
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val exp = input.rs1.exponent +^ input.rs2.exponent - ((1 << p.internalExponentSize - 1) - 1)
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}
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val norm = new Area{
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val needShift = math.mulC.msb
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val exp = math.exp + U(needShift)
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val man = needShift ? math.mulC(p.internalMantissaSize + 1, p.internalMantissaSize bits) | math.mulC(p.internalMantissaSize, p.internalMantissaSize bits)
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val output = FpuFloat(p.internalExponentSize, p.internalMantissaSize)
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output.sign := input.rs1.sign ^ input.rs2.sign
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output.exponent := exp.resized
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output.mantissa := man
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}
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val output = Stream(WriteInput())
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output.valid := input.valid && !input.add
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output.source := input.source
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output.lockId := input.lockId
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output.rd := input.rd
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output.value := norm.output
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decode.mulToAdd.valid := input.valid && input.add
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decode.mulToAdd.source := input.source
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decode.mulToAdd.rs1.mantissa := norm.output.mantissa
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decode.mulToAdd.rs1.exponent := norm.output.exponent
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decode.mulToAdd.rs1.sign := norm.output.sign ^ input.minus
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decode.mulToAdd.rs2 := input.rs3
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decode.mulToAdd.rd := input.rd
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decode.mulToAdd.lockId := input.lockId
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input.ready := (input.add ? decode.mulToAdd.ready | output.ready)
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}
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val add = new Area{
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val input = decode.add.stage()
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val shifter = new Area {
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val exp21 = input.rs2.exponent - input.rs1.exponent
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val rs1ExponentBigger = exp21.msb
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val rs1ExponentEqual = input.rs1.exponent === input.rs2.exponent
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val rs1MantissaBigger = input.rs1.mantissa > input.rs2.mantissa
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val absRs1Bigger = rs1ExponentBigger|| rs1ExponentEqual && rs1MantissaBigger
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val shiftBy = rs1ExponentBigger ? (0-exp21) | exp21
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//Note that rs1ExponentBigger can be replaced by absRs1Bigger bellow to avoid xsigned two complement in math block at expense of combinatorial path
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val xySign = absRs1Bigger ? input.rs1.sign | input.rs2.sign
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val xSign = xySign ^ (rs1ExponentBigger ? input.rs1.sign | input.rs2.sign)
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val ySign = xySign ^ (rs1ExponentBigger ? input.rs2.sign | input.rs1.sign)
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val xMantissa = U"1" @@ (rs1ExponentBigger ? input.rs1.mantissa | input.rs2.mantissa)
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val yMantissaUnshifted = U"1" @@ (rs1ExponentBigger ? input.rs2.mantissa | input.rs1.mantissa)
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val yMantissa = yMantissaUnshifted >> shiftBy
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val xyExponent = rs1ExponentBigger ? input.rs1.exponent | input.rs2.exponent
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}
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val math = new Area {
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def xSign = shifter.xSign
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def ySign = shifter.ySign
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def xMantissa = shifter.xMantissa
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def yMantissa = shifter.yMantissa
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def xyExponent = shifter.xyExponent
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def xySign = shifter.xySign
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val xSigned = xMantissa.twoComplement(xSign)
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val ySigned = yMantissa.twoComplement(ySign)
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val xyMantissa = U(xSigned +^ ySigned).trim(1 bits)
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}
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val norm = new Area{
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def xyExponent = math.xyExponent
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def xyMantissa = math.xyMantissa
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def xySign = math.xySign
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val shiftOh = OHMasking.first(xyMantissa.asBools.reverse)
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val shift = OHToUInt(shiftOh)
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val mantissa = (xyMantissa |<< shift) >> 1
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val exponent = xyExponent - shift + 1
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}
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val output = input.swapPayload(WriteInput())
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output.source := input.source
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output.lockId := input.lockId
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output.rd := input.rd
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output.value.sign := norm.xySign
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output.value.mantissa := norm.mantissa.resized
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output.value.exponent := norm.exponent
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}
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val write = new Area{
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val port = rf.ram.writePort
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port.valid := False
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port.payload.assignDontCare()
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val lockFree = Flow(lockIdType)
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lockFree.valid := port.fire
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lockFree.payload.assignDontCare()
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load.output.ready := False
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mul.output.ready := False
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add.output.ready := True
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io.port.commit.ready := False
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when(add.output.valid) {
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port.valid := True
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port.address := add.output.source @@ add.output.rd
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port.data := add.output.value
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lockFree.payload := add.output.lockId
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} elsewhen(mul.output.valid) {
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port.valid := True
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port.address := mul.output.source @@ mul.output.rd
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port.data := mul.output.value
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mul.output.ready := True
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lockFree.payload := mul.output.lockId
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} elsewhen(load.output.valid && io.port.commit.valid) {
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port.valid := io.port.commit.write
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port.address := load.output.source @@ load.output.rd
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port.data.assignFromBits(io.port.commit.value)
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load.output.ready := True
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io.port.commit.ready := True
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lockFree.payload := load.output.lockId
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}
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when(lockFree.fire){
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for(i <- 0 until rfLockCount) when(lockFree.payload === i){
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rf.lock(i).valid := False
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}
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}
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}
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}
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object StreamFifoMultiChannelBench extends App{
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val payloadType = HardType(Bits(8 bits))
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class Fpu(name : String, p : FpuParameter) extends Rtl{
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override def getName(): String = "Fpu_" + name
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override def getRtlPath(): String = getName() + ".v"
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SpinalVerilog(new FpuCore(p){
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setDefinitionName(Fpu.this.getName())
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})
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}
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val rtls = ArrayBuffer[Fpu]()
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rtls += new Fpu(
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"32",
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FpuParameter(
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internalMantissaSize = 23,
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withDouble = false,
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sourceWidth = 0
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)
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)
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rtls += new Fpu(
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"64",
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FpuParameter(
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internalMantissaSize = 52,
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withDouble = true,
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sourceWidth = 0
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)
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)
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val targets = XilinxStdTargets()// ++ AlteraStdTargets()
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Bench(rtls, targets)
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}
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@ -0,0 +1,77 @@
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package vexriscv.ip.fpu
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import spinal.core._
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import spinal.lib._
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object Fpu{
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object Function{
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val MUL = 0
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val ADD = 1
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}
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}
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case class FpuFloat(exponentSize: Int,
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mantissaSize: Int) extends Bundle {
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val mantissa = UInt(mantissaSize bits)
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val exponent = UInt(exponentSize bits)
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val sign = Bool
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}
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case class FpuOpcode(p : FpuParameter) extends SpinalEnum{
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val LOAD, STORE, MUL, ADD, FMA, I2F, F2I, CMP = newElement()
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}
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case class FpuParameter( internalMantissaSize : Int,
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withDouble : Boolean,
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sourceWidth : Int){
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val storeLoadType = HardType(Bits(if(withDouble) 64 bits else 32 bits))
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val internalExponentSize = if(withDouble) 11 else 8
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val internalFloating = HardType(FpuFloat(exponentSize = internalExponentSize, mantissaSize = internalMantissaSize))
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// val opcode = HardType(UInt(2 bits))
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val source = HardType(UInt(sourceWidth bits))
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val rfAddress = HardType(UInt(5 bits))
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val Opcode = new FpuOpcode(this)
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val Format = new SpinalEnum{
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val FLOAT = newElement()
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val DOUBLE = withDouble generate newElement()
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}
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}
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case class FpuCmd(p : FpuParameter) extends Bundle{
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val source = UInt(p.sourceWidth bits)
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val opcode = p.Opcode()
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val value = Bits(32 bits) // Int to float
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val function = Bits(3 bits) // Int to float
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val rs1, rs2, rs3 = p.rfAddress()
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val rd = p.rfAddress()
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val format = p.Format()
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}
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case class FpuCommit(p : FpuParameter) extends Bundle{
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val source = UInt(p.sourceWidth bits)
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val write = Bool()
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val value = p.storeLoadType() // IEEE 754 load
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}
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case class FpuRsp(p : FpuParameter) extends Bundle{
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val source = UInt(p.sourceWidth bits)
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val value = p.storeLoadType() // IEEE754 store || Integer
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}
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case class FpuPort(p : FpuParameter) extends Bundle with IMasterSlave {
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val cmd = Stream(FpuCmd(p))
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val commit = Stream(FpuCommit(p))
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val rsp = Stream(FpuRsp(p))
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override def asMaster(): Unit = {
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master(cmd, commit)
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slave(rsp)
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}
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}
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@ -0,0 +1,245 @@
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package vexriscv.ip.fpu
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import java.lang
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import org.scalatest.FunSuite
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import spinal.core.SpinalEnumElement
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import spinal.core.sim._
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import spinal.lib.experimental.math.Floating
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import spinal.lib.sim._
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import scala.collection.mutable
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import scala.collection.mutable.ArrayBuffer
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import scala.util.Random
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class FpuTest extends FunSuite{
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||||
|
||||
|
||||
test("directed"){
|
||||
val p = FpuParameter(
|
||||
internalMantissaSize = 23,
|
||||
withDouble = false,
|
||||
sourceWidth = 0
|
||||
)
|
||||
|
||||
SimConfig.withFstWave.compile(new FpuCore(p)).doSim(seed = 42){ dut =>
|
||||
dut.clockDomain.forkStimulus(10)
|
||||
|
||||
|
||||
|
||||
|
||||
val cpus = for(id <- 0 until 1 << p.sourceWidth) yield new {
|
||||
val cmdQueue = mutable.Queue[FpuCmd => Unit]()
|
||||
val commitQueue = mutable.Queue[FpuCommit => Unit]()
|
||||
val rspQueue = mutable.Queue[FpuRsp => Unit]()
|
||||
|
||||
def loadRaw(rd : Int, value : BigInt): Unit ={
|
||||
cmdQueue += {cmd =>
|
||||
cmd.source #= id
|
||||
cmd.opcode #= cmd.opcode.spinalEnum.LOAD
|
||||
cmd.value.randomize()
|
||||
cmd.rs1.randomize()
|
||||
cmd.rs2.randomize()
|
||||
cmd.rs3.randomize()
|
||||
cmd.rd #= rd
|
||||
}
|
||||
commitQueue += {cmd =>
|
||||
cmd.source #= id
|
||||
cmd.write #= true
|
||||
cmd.value #= value
|
||||
}
|
||||
}
|
||||
|
||||
def load(rd : Int, value : Float): Unit ={
|
||||
loadRaw(rd, lang.Float.floatToIntBits(value).toLong & 0xFFFFFFFFl)
|
||||
}
|
||||
|
||||
def storeRaw(rs : Int)(body : FpuRsp => Unit): Unit ={
|
||||
cmdQueue += {cmd =>
|
||||
cmd.source #= id
|
||||
cmd.opcode #= cmd.opcode.spinalEnum.STORE
|
||||
cmd.value.randomize()
|
||||
cmd.rs1.randomize()
|
||||
cmd.rs2 #= rs
|
||||
cmd.rs3.randomize()
|
||||
cmd.rd.randomize()
|
||||
}
|
||||
|
||||
rspQueue += body
|
||||
}
|
||||
|
||||
def storeFloat(rs : Int)(body : Float => Unit): Unit ={
|
||||
storeRaw(rs){rsp => body(lang.Float.intBitsToFloat(rsp.value.toLong.toInt))}
|
||||
}
|
||||
|
||||
def mul(rd : Int, rs1 : Int, rs2 : Int): Unit ={
|
||||
cmdQueue += {cmd =>
|
||||
cmd.source #= id
|
||||
cmd.opcode #= cmd.opcode.spinalEnum.MUL
|
||||
cmd.value.randomize()
|
||||
cmd.rs1 #= rs1
|
||||
cmd.rs2 #= rs2
|
||||
cmd.rs3.randomize()
|
||||
cmd.rd #= rd
|
||||
}
|
||||
}
|
||||
|
||||
def add(rd : Int, rs1 : Int, rs2 : Int): Unit ={
|
||||
cmdQueue += {cmd =>
|
||||
cmd.source #= id
|
||||
cmd.opcode #= cmd.opcode.spinalEnum.ADD
|
||||
cmd.value.randomize()
|
||||
cmd.rs1 #= rs1
|
||||
cmd.rs2 #= rs2
|
||||
cmd.rs3.randomize()
|
||||
cmd.rd #= rd
|
||||
}
|
||||
}
|
||||
|
||||
def fma(rd : Int, rs1 : Int, rs2 : Int, rs3 : Int): Unit ={
|
||||
cmdQueue += {cmd =>
|
||||
cmd.source #= id
|
||||
cmd.opcode #= cmd.opcode.spinalEnum.FMA
|
||||
cmd.value.randomize()
|
||||
cmd.rs1 #= rs1
|
||||
cmd.rs2 #= rs2
|
||||
cmd.rs3 #= rs3
|
||||
cmd.rd #= rd
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
StreamDriver(dut.io.port.cmd ,dut.clockDomain){payload =>
|
||||
cpus.map(_.cmdQueue).filter(_.nonEmpty).toSeq match {
|
||||
case Nil => false
|
||||
case l => {
|
||||
l.randomPick().dequeue().apply(payload)
|
||||
true
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
StreamDriver(dut.io.port.commit ,dut.clockDomain){payload =>
|
||||
cpus.map(_.commitQueue).filter(_.nonEmpty).toSeq match {
|
||||
case Nil => false
|
||||
case l => {
|
||||
l.randomPick().dequeue().apply(payload)
|
||||
true
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
StreamMonitor(dut.io.port.rsp, dut.clockDomain){payload =>
|
||||
cpus(payload.source.toInt).rspQueue.dequeue().apply(payload)
|
||||
}
|
||||
|
||||
StreamReadyRandomizer(dut.io.port.rsp, dut.clockDomain)
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
val stim = for(cpu <- cpus) yield fork {
|
||||
import cpu._
|
||||
|
||||
class RegAllocator(){
|
||||
var value = 0
|
||||
|
||||
def allocate(): Int ={
|
||||
while(true){
|
||||
val rand = Random.nextInt(32)
|
||||
val mask = 1 << rand
|
||||
if((value & mask) == 0) {
|
||||
value |= mask
|
||||
return rand
|
||||
}
|
||||
}
|
||||
0
|
||||
}
|
||||
}
|
||||
def checkFloat(ref : Float, dut : Float): Boolean ={
|
||||
ref.abs * 1.0001 > dut.abs && ref.abs * 0.9999 < dut.abs && ref.signum == dut.signum
|
||||
}
|
||||
|
||||
def randomFloat(): Float ={
|
||||
Random.nextFloat() * 1e2f * (if(Random.nextBoolean()) -1f else 1f)
|
||||
}
|
||||
|
||||
def testAdd(a : Float, b : Float): Unit ={
|
||||
val rs = new RegAllocator()
|
||||
val rs1, rs2, rs3 = rs.allocate()
|
||||
val rd = Random.nextInt(32)
|
||||
load(rs1, a)
|
||||
load(rs2, b)
|
||||
|
||||
add(rd,rs1,rs2)
|
||||
storeFloat(rd){v =>
|
||||
val ref = a+b
|
||||
println(f"$a + $b = $v, $ref")
|
||||
assert(checkFloat(ref, v))
|
||||
}
|
||||
}
|
||||
|
||||
def testMul(a : Float, b : Float): Unit ={
|
||||
val rs = new RegAllocator()
|
||||
val rs1, rs2, rs3 = rs.allocate()
|
||||
val rd = Random.nextInt(32)
|
||||
load(rs1, a)
|
||||
load(rs2, b)
|
||||
|
||||
mul(rd,rs1,rs2)
|
||||
storeFloat(rd){v =>
|
||||
val ref = a*b
|
||||
println(f"$a * $b = $v, $ref")
|
||||
assert(checkFloat(ref, v))
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
def testFma(a : Float, b : Float, c : Float): Unit ={
|
||||
val rs = new RegAllocator()
|
||||
val rs1, rs2, rs3 = rs.allocate()
|
||||
val rd = Random.nextInt(32)
|
||||
load(rs1, a)
|
||||
load(rs2, b)
|
||||
load(rs3, c)
|
||||
|
||||
fma(rd,rs1,rs2,rs3)
|
||||
storeFloat(rd){v =>
|
||||
val ref = a * b + c
|
||||
println(f"$a * $b + $c = $v, $ref")
|
||||
assert(checkFloat(ref, v))
|
||||
}
|
||||
}
|
||||
|
||||
// testAdd(0.1f, 1.6f)
|
||||
// testMul(0.1f, 1.6f)
|
||||
testFma(1.1f, 2.2f, 3.0f)
|
||||
|
||||
for(i <- 0 until 1000){
|
||||
testAdd(randomFloat(), randomFloat())
|
||||
}
|
||||
for(i <- 0 until 1000){
|
||||
testMul(randomFloat(), randomFloat())
|
||||
}
|
||||
for(i <- 0 until 1000){
|
||||
testFma(randomFloat(), randomFloat(), randomFloat())
|
||||
}
|
||||
for(i <- 0 until 1000){
|
||||
val tests = ArrayBuffer[() => Unit]()
|
||||
tests += (() =>{testAdd(randomFloat(), randomFloat())})
|
||||
tests += (() =>{testMul(randomFloat(), randomFloat())})
|
||||
tests += (() =>{testFma(randomFloat(), randomFloat(), randomFloat())})
|
||||
tests.randomPick().apply()
|
||||
}
|
||||
|
||||
waitUntil(cpu.rspQueue.isEmpty)
|
||||
}
|
||||
|
||||
|
||||
stim.foreach(_.join())
|
||||
dut.clockDomain.waitSampling(100)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,39 @@
|
|||
package vexriscv.ip.fpu
|
||||
|
||||
object MiaouDiv extends App{
|
||||
val input = 2.5
|
||||
var output = 1/(input*0.95)
|
||||
// def x = output
|
||||
// def y = input
|
||||
|
||||
def y = output
|
||||
def x = input
|
||||
|
||||
for(i <- 0 until 10) {
|
||||
output = 2 * y - x * y * y
|
||||
println(output)
|
||||
}
|
||||
|
||||
|
||||
//output = x*output
|
||||
println(1/input)
|
||||
}
|
||||
|
||||
object MiaouSqrt extends App{
|
||||
val input = 2.0
|
||||
var output = 1/Math.sqrt(input*0.95)
|
||||
// def x = output
|
||||
// def y = input
|
||||
|
||||
def y = output
|
||||
def x = input
|
||||
|
||||
for(i <- 0 until 10) {
|
||||
output = y*(1.5-x*y*y/2)
|
||||
println(output)
|
||||
}
|
||||
|
||||
output = x*output
|
||||
println(output)
|
||||
println(s"ref ${Math.sqrt(input)}")
|
||||
}
|
||||
Loading…
Reference in New Issue