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VexRiscv
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Fix FPU access port instanciation when not needed

This commit is contained in:
Charles Papon 2023-03-14 15:23:04 +08:00
parent 25eda80fee
commit 876222d886
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -645,7 +645,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
xretAwayFromMachine = False xretAwayFromMachine = False
if(pipeline.config.FLEN == 64) pipeline.service(classOf[FpuPlugin]).requireAccessPort() if(withPrivilegedDebug && pipeline.config.FLEN == 64) pipeline.service(classOf[FpuPlugin]).requireAccessPort()
injectionPort = withPrivilegedDebug generate pipeline.service(classOf[IBusFetcher]).getInjectionPort().setCompositeName(this, "injectionPort") injectionPort = withPrivilegedDebug generate pipeline.service(classOf[IBusFetcher]).getInjectionPort().setCompositeName(this, "injectionPort")
debugMode = withPrivilegedDebug generate Bool().setName("debugMode") debugMode = withPrivilegedDebug generate Bool().setName("debugMode")
@ -735,7 +735,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
bus.hartToDm.data := execute.input(SRC1) bus.hartToDm.data := execute.input(SRC1)
} }
val withDebugFpuAccess = pipeline.config.FLEN == 64 val withDebugFpuAccess = withPrivilegedDebug && pipeline.config.FLEN == 64
val dataCsrw = new Area{ val dataCsrw = new Area{
val value = Vec.fill(1+withDebugFpuAccess.toInt)(Reg(Bits(32 bits))) val value = Vec.fill(1+withDebugFpuAccess.toInt)(Reg(Bits(32 bits)))