Fix RVC instruction cache xtval allignement

2019-04-05 01:08:57 +02:00 · 2019-04-05 01:08:57 +02:00 · 888e1c0b8a
parent 8e6010fd71
commit 888e1c0b8a
1 changed files with 1 additions and 1 deletions
--- a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
@ -207,7 +207,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
        if (catchSomething) {
          decodeExceptionPort.valid := False
          decodeExceptionPort.code.assignDontCare()
-          decodeExceptionPort.badAddr := cacheRsp.pc
+          decodeExceptionPort.badAddr := cacheRsp.pc(31 downto 2) @@ "00"

          if(catchIllegalAccess) when(cacheRsp.isValid && cacheRsp.mmuException && !issueDetected) {
            issueDetected \= True