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Fix RVC instruction cache xtval allignement

This commit is contained in:
Charles Papon 2019-04-05 01:08:57 +02:00
parent 8e6010fd71
commit 888e1c0b8a
1 changed files with 1 additions and 1 deletions
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2
src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala
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@ -207,7 +207,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
if (catchSomething) { if (catchSomething) {
decodeExceptionPort.valid := False decodeExceptionPort.valid := False
decodeExceptionPort.code.assignDontCare() decodeExceptionPort.code.assignDontCare()
decodeExceptionPort.badAddr := cacheRsp.pc decodeExceptionPort.badAddr := cacheRsp.pc(31 downto 2) @@ "00"
if(catchIllegalAccess) when(cacheRsp.isValid && cacheRsp.mmuException && !issueDetected) { if(catchIllegalAccess) when(cacheRsp.isValid && cacheRsp.mmuException && !issueDetected) {
issueDetected \= True issueDetected \= True