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Fix Mhz -> MHz in Dhrystone benchmark report generation

This commit is contained in:
Marc Emery 2024-06-17 22:00:19 +02:00
parent 7beb9887a6
commit 8968b5a3fa
1 changed files with 1 additions and 1 deletions
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2
src/test/scala/vexriscv/DhrystoneBench.scala
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@ -45,7 +45,7 @@ class DhrystoneBench extends AnyFunSuite {
val coremarkIterations = intFind.findFirstIn("Iterations \\: (\\d+.?)+".r.findAllIn(str).toList.last).get.toDouble
val coremarkHzs = intFind.findFirstIn("DCLOCKS_PER_SEC=(\\d+.?)+".r.findAllIn(str).toList.last).get.toDouble
val coremarkPerMhz = 1e6 * coremarkIterations / coremarkTicks
report ++= s"$name -> $dmips DMIPS/Mhz $coremarkPerMhz Coremark/Mhz\n"
report ++= s"$name -> $dmips DMIPS/MHz $coremarkPerMhz Coremark/MHz\n"
}
}