Add Bmb support for i$/d$
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@ -5,8 +5,10 @@ import spinal.core._
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import spinal.lib._
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import spinal.lib.bus.amba4.axi.{Axi4Config, Axi4Shared}
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import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig}
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import spinal.lib.bus.bmb.{Bmb, BmbParameter}
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import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig}
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import spinal.lib.bus.simple._
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import vexriscv.plugin.DBusSimpleBus
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case class DataCacheConfig(cacheSize : Int,
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@ -64,6 +66,18 @@ case class DataCacheConfig(cacheSize : Int,
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useBTE = true,
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useCTI = true
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)
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def getBmbParameter() = BmbParameter(
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addressWidth = 32,
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dataWidth = 32,
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lengthWidth = log2Up(this.bytePerLine),
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sourceWidth = 0,
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contextWidth = 1,
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canRead = true,
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canWrite = true,
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alignment = BmbParameter.BurstAlignement.LENGTH,
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maximumPendingTransactionPerId = Int.MaxValue
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)
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}
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object DataCacheCpuExecute{
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@ -298,6 +312,30 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
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bus
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}
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def toBmb() : Bmb = {
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val pipelinedMemoryBusConfig = p.getBmbParameter()
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val bus = Bmb(pipelinedMemoryBusConfig)
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bus.cmd.valid := cmd.valid
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bus.cmd.last := cmd.last
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bus.cmd.context(0) := cmd.wr
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bus.cmd.opcode := (cmd.wr ? B(Bmb.Cmd.Opcode.WRITE) | B(Bmb.Cmd.Opcode.READ))
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bus.cmd.address := cmd.address.resized
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bus.cmd.data := cmd.data
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bus.cmd.length := cmd.length << 2 //TODO better sub word access
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bus.cmd.mask := cmd.mask
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cmd.ready := bus.cmd.ready
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rsp.valid := bus.rsp.valid && !bus.rsp.context(0)
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rsp.data := bus.rsp.data
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rsp.error := bus.rsp.isError
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bus.rsp.ready := True
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bus
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}
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}
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@ -5,8 +5,10 @@ import spinal.core._
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import spinal.lib._
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import spinal.lib.bus.amba4.axi.{Axi4Config, Axi4ReadOnly}
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import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig}
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import spinal.lib.bus.bmb.{Bmb, BmbParameter}
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import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig}
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import spinal.lib.bus.simple._
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import vexriscv.plugin.{IBusSimpleBus, IBusSimplePlugin}
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case class InstructionCacheConfig( cacheSize : Int,
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@ -64,6 +66,18 @@ case class InstructionCacheConfig( cacheSize : Int,
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useBTE = true,
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useCTI = true
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)
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def getBmbParameter() = BmbParameter(
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addressWidth = 32,
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dataWidth = 32,
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lengthWidth = log2Up(this.bytePerLine),
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sourceWidth = 0,
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contextWidth = 0,
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canRead = true,
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canWrite = false,
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alignment = BmbParameter.BurstAlignement.LENGTH,
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maximumPendingTransactionPerId = 1
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)
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}
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@ -233,6 +247,21 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
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rsp.error := False //TODO
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bus
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}
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def toBmb() : Bmb = {
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val busParameter = p.getBmbParameter
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val bus = Bmb(busParameter)
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bus.cmd.arbitrationFrom(cmd)
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bus.cmd.opcode := Bmb.Cmd.Opcode.READ
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bus.cmd.address := cmd.address.resized
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bus.cmd.length := (1 << p.bytePerLine) - 1
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bus.cmd.last := True
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rsp.valid := bus.rsp.valid
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rsp.data := bus.rsp.data
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rsp.error := bus.rsp.isError
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bus.rsp.ready := True
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bus
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}
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}
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@ -18,7 +18,7 @@ class DAxiCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An
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}
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}
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class DBusCachedPlugin(config : DataCacheConfig,
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class DBusCachedPlugin(val config : DataCacheConfig,
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memoryTranslatorPortConfig : Any = null,
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dBusCmdMasterPipe : Boolean = false,
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dBusCmdSlavePipe : Boolean = false,
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@ -31,7 +31,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l,
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historyRamSizeLog2 : Int = 10,
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compressedGen : Boolean = false,
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keepPcPlus4 : Boolean = false,
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config : InstructionCacheConfig,
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val config : InstructionCacheConfig,
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memoryTranslatorPortConfig : Any = null,
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injectorStage : Boolean = false,
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withoutInjectorStage : Boolean = false,
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