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Update readme with GCC changes from the VexRiscvSocSoftware repo

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Charles Papon 2017-08-14 11:40:33 +02:00
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commit 8fbd777794
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README.md
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@ -295,7 +295,13 @@ There is some scripts to generate the SoC and call the icestorm toolchain there
## Build the RISC-V GCC ## Build the RISC-V GCC
To install in /opt/ the rv32i and rv32im gcc, do the following (will take hours): In fact, you can find some prebuild GCC : <br>
- https://www.sifive.com/products/tools/ => SiFive GNU Embedded Toolchain
The VexRiscvSocSoftware makefiles are expecting to find this prebuild version in /opt/rv/__contentOfThisPreBuild__
But if you want to compile from sources in /opt/ the rv32i and rv32im gcc, do the following (will take hours):
```sh ```sh
# Be carefull, sometime the git clone has issue to successfully clone riscv-gnu-toolchain. # Be carefull, sometime the git clone has issue to successfully clone riscv-gnu-toolchain.