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DivPlugin is now based MulDivIterativePlugin (Smaller)

This commit is contained in:
Dolu1990 2018-03-10 13:31:35 +01:00
parent f133e69fed
commit 91031f8d75
1 changed files with 69 additions and 65 deletions
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134
src/main/scala/vexriscv/plugin/DivPlugin.scala
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@ -2,70 +2,74 @@ package vexriscv.plugin
import vexriscv.{VexRiscv, _} import vexriscv.{VexRiscv, _}
import spinal.core._ import spinal.core._
import spinal.lib.math.MixedDivider
class DivPlugin extends Plugin[VexRiscv]{ // DivPlugin was by the past a standalone plugin, but now it use the MulDivIterativePlugin implementation
object IS_DIV extends Stageable(Bool) class DivPlugin extends MulDivIterativePlugin(genMul = false, genDiv = true, mulUnroolFactor = 1, divUnroolFactor = 1)
override def setup(pipeline: VexRiscv): Unit = { //import spinal.lib.math.MixedDivider
import Riscv._ //
import pipeline.config._ //class DivPlugin extends Plugin[VexRiscv]{
// object IS_DIV extends Stageable(Bool)
val actions = List[(Stageable[_ <: BaseType],Any)]( //
SRC1_CTRL -> Src1CtrlEnum.RS, // override def setup(pipeline: VexRiscv): Unit = {
SRC2_CTRL -> Src2CtrlEnum.RS, // import Riscv._
REGFILE_WRITE_VALID -> True, // import pipeline.config._
BYPASSABLE_EXECUTE_STAGE -> False, //
BYPASSABLE_MEMORY_STAGE -> True, // val actions = List[(Stageable[_ <: BaseType],Any)](
RS1_USE -> True, // SRC1_CTRL -> Src1CtrlEnum.RS,
RS2_USE -> True, // SRC2_CTRL -> Src2CtrlEnum.RS,
IS_DIV -> True // REGFILE_WRITE_VALID -> True,
) // BYPASSABLE_EXECUTE_STAGE -> False,
// BYPASSABLE_MEMORY_STAGE -> True,
val decoderService = pipeline.service(classOf[DecoderService]) // RS1_USE -> True,
decoderService.addDefault(IS_DIV, False) // RS2_USE -> True,
decoderService.add(List( // IS_DIV -> True
DIVX -> actions // )
)) //
// val decoderService = pipeline.service(classOf[DecoderService])
} // decoderService.addDefault(IS_DIV, False)
// decoderService.add(List(
override def build(pipeline: VexRiscv): Unit = { // DIVX -> actions
import pipeline._ // ))
import pipeline.config._ //
// }
val divider = new MixedDivider(32, 32, true) //cmd >-> rsp //
// override def build(pipeline: VexRiscv): Unit = {
//Send request to the divider component // import pipeline._
execute plug new Area { // import pipeline.config._
import execute._ //
// val divider = new MixedDivider(32, 32, true) //cmd >-> rsp
divider.io.cmd.valid := False //
divider.io.cmd.numerator := input(SRC1) // //Send request to the divider component
divider.io.cmd.denominator := input(SRC2) // execute plug new Area {
divider.io.cmd.signed := !input(INSTRUCTION)(12) // import execute._
//
when(arbitration.isValid && input(IS_DIV)) { // divider.io.cmd.valid := False
divider.io.cmd.valid := !arbitration.isStuckByOthers && !arbitration.removeIt // divider.io.cmd.numerator := input(SRC1)
arbitration.haltItself := memory.arbitration.isValid && memory.input(IS_DIV) // divider.io.cmd.denominator := input(SRC2)
} // divider.io.cmd.signed := !input(INSTRUCTION)(12)
} //
// when(arbitration.isValid && input(IS_DIV)) {
//Collect response from the divider component, REGFILE_WRITE_DATA overriding // divider.io.cmd.valid := !arbitration.isStuckByOthers && !arbitration.removeIt
memory plug new Area{ // arbitration.haltItself := memory.arbitration.isValid && memory.input(IS_DIV)
import memory._ // }
// }
divider.io.flush := memory.arbitration.removeIt //
divider.io.rsp.ready := !arbitration.isStuckByOthers // //Collect response from the divider component, REGFILE_WRITE_DATA overriding
// memory plug new Area{
when(arbitration.isValid && input(IS_DIV)) { // import memory._
arbitration.haltItself := !divider.io.rsp.valid //
// divider.io.flush := memory.arbitration.removeIt
output(REGFILE_WRITE_DATA) := Mux(input(INSTRUCTION)(13), divider.io.rsp.remainder, divider.io.rsp.quotient).asBits // divider.io.rsp.ready := !arbitration.isStuckByOthers
} //
// when(arbitration.isValid && input(IS_DIV)) {
// arbitration.haltItself := !divider.io.rsp.valid
divider.io.rsp.payload.error.allowPruning //
} // output(REGFILE_WRITE_DATA) := Mux(input(INSTRUCTION)(13), divider.io.rsp.remainder, divider.io.rsp.quotient).asBits
} // }
} //
//
// divider.io.rsp.payload.error.allowPruning
// }
// }
// }