DivPlugin is now based MulDivIterativePlugin (Smaller)
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@ -2,70 +2,74 @@ package vexriscv.plugin
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import vexriscv.{VexRiscv, _}
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import spinal.core._
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import spinal.lib.math.MixedDivider
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class DivPlugin extends Plugin[VexRiscv]{
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object IS_DIV extends Stageable(Bool)
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// DivPlugin was by the past a standalone plugin, but now it use the MulDivIterativePlugin implementation
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class DivPlugin extends MulDivIterativePlugin(genMul = false, genDiv = true, mulUnroolFactor = 1, divUnroolFactor = 1)
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override def setup(pipeline: VexRiscv): Unit = {
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import Riscv._
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import pipeline.config._
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val actions = List[(Stageable[_ <: BaseType],Any)](
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SRC1_CTRL -> Src1CtrlEnum.RS,
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SRC2_CTRL -> Src2CtrlEnum.RS,
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REGFILE_WRITE_VALID -> True,
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BYPASSABLE_EXECUTE_STAGE -> False,
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BYPASSABLE_MEMORY_STAGE -> True,
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RS1_USE -> True,
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RS2_USE -> True,
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IS_DIV -> True
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)
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val decoderService = pipeline.service(classOf[DecoderService])
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decoderService.addDefault(IS_DIV, False)
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decoderService.add(List(
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DIVX -> actions
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))
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}
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override def build(pipeline: VexRiscv): Unit = {
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import pipeline._
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import pipeline.config._
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val divider = new MixedDivider(32, 32, true) //cmd >-> rsp
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//Send request to the divider component
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execute plug new Area {
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import execute._
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divider.io.cmd.valid := False
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divider.io.cmd.numerator := input(SRC1)
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divider.io.cmd.denominator := input(SRC2)
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divider.io.cmd.signed := !input(INSTRUCTION)(12)
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when(arbitration.isValid && input(IS_DIV)) {
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divider.io.cmd.valid := !arbitration.isStuckByOthers && !arbitration.removeIt
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arbitration.haltItself := memory.arbitration.isValid && memory.input(IS_DIV)
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}
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}
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//Collect response from the divider component, REGFILE_WRITE_DATA overriding
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memory plug new Area{
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import memory._
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divider.io.flush := memory.arbitration.removeIt
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divider.io.rsp.ready := !arbitration.isStuckByOthers
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when(arbitration.isValid && input(IS_DIV)) {
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arbitration.haltItself := !divider.io.rsp.valid
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output(REGFILE_WRITE_DATA) := Mux(input(INSTRUCTION)(13), divider.io.rsp.remainder, divider.io.rsp.quotient).asBits
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}
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divider.io.rsp.payload.error.allowPruning
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}
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}
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}
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//import spinal.lib.math.MixedDivider
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//
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//class DivPlugin extends Plugin[VexRiscv]{
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// object IS_DIV extends Stageable(Bool)
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//
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// override def setup(pipeline: VexRiscv): Unit = {
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// import Riscv._
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// import pipeline.config._
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//
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// val actions = List[(Stageable[_ <: BaseType],Any)](
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// SRC1_CTRL -> Src1CtrlEnum.RS,
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// SRC2_CTRL -> Src2CtrlEnum.RS,
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// REGFILE_WRITE_VALID -> True,
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// BYPASSABLE_EXECUTE_STAGE -> False,
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// BYPASSABLE_MEMORY_STAGE -> True,
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// RS1_USE -> True,
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// RS2_USE -> True,
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// IS_DIV -> True
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// )
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//
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// val decoderService = pipeline.service(classOf[DecoderService])
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// decoderService.addDefault(IS_DIV, False)
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// decoderService.add(List(
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// DIVX -> actions
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// ))
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//
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// }
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//
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// override def build(pipeline: VexRiscv): Unit = {
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// import pipeline._
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// import pipeline.config._
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//
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// val divider = new MixedDivider(32, 32, true) //cmd >-> rsp
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//
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// //Send request to the divider component
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// execute plug new Area {
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// import execute._
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//
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// divider.io.cmd.valid := False
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// divider.io.cmd.numerator := input(SRC1)
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// divider.io.cmd.denominator := input(SRC2)
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// divider.io.cmd.signed := !input(INSTRUCTION)(12)
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//
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// when(arbitration.isValid && input(IS_DIV)) {
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// divider.io.cmd.valid := !arbitration.isStuckByOthers && !arbitration.removeIt
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// arbitration.haltItself := memory.arbitration.isValid && memory.input(IS_DIV)
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// }
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// }
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//
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// //Collect response from the divider component, REGFILE_WRITE_DATA overriding
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// memory plug new Area{
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// import memory._
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//
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// divider.io.flush := memory.arbitration.removeIt
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// divider.io.rsp.ready := !arbitration.isStuckByOthers
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//
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// when(arbitration.isValid && input(IS_DIV)) {
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// arbitration.haltItself := !divider.io.rsp.valid
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//
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// output(REGFILE_WRITE_DATA) := Mux(input(INSTRUCTION)(13), divider.io.rsp.remainder, divider.io.rsp.quotient).asBits
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// }
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//
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//
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// divider.io.rsp.payload.error.allowPruning
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// }
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// }
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// }
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