litex smp cluster now use OO decoder
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@ -274,19 +274,18 @@ case class VexRiscvLitexSmpCluster(p : VexRiscvLitexSmpClusterParameter,
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cluster.io.timerInterrupts <> B(clint.harts.map(_.timerInterrupt))
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cluster.io.timerInterrupts <> B(clint.harts.map(_.timerInterrupt))
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cluster.io.softwareInterrupts <> B(clint.harts.map(_.softwareInterrupt))
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cluster.io.softwareInterrupts <> B(clint.harts.map(_.softwareInterrupt))
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//TODO
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val dBusDecoder = BmbDecoderOutOfOrder(
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// val dBusDecoder = BmbDecoderOutOfOrder(
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// p = cluster.io.dMem.p,
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// mappings = Seq(DefaultMapping, p.liteDramMapping),
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// capabilities = Seq(cluster.io.dMem.p, cluster.io.dMem.p),
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// pendingRspTransactionMax = 32
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// )
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val dBusDecoder = BmbDecoder(
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p = cluster.io.dMem.p,
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p = cluster.io.dMem.p,
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mappings = Seq(DefaultMapping, p.liteDramMapping),
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mappings = Seq(DefaultMapping, p.liteDramMapping),
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capabilities = Seq(cluster.io.dMem.p, cluster.io.dMem.p),
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capabilities = Seq(cluster.io.dMem.p, cluster.io.dMem.p),
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pendingMax = 31
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pendingRspTransactionMax = 32
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)
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)
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// val dBusDecoder = BmbDecoderOut(
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// p = cluster.io.dMem.p,
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// mappings = Seq(DefaultMapping, p.liteDramMapping),
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// capabilities = Seq(cluster.io.dMem.p, cluster.io.dMem.p),
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// pendingMax = 31
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// )
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dBusDecoder.io.input << cluster.io.dMem.pipelined(cmdValid = true, cmdReady = true, rspValid = true)
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dBusDecoder.io.input << cluster.io.dMem.pipelined(cmdValid = true, cmdReady = true, rspValid = true)
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val dMemBridge = io.dMem.fromBmb(dBusDecoder.io.outputs(1), wdataFifoSize = 32, rdataFifoSize = 32)
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val dMemBridge = io.dMem.fromBmb(dBusDecoder.io.outputs(1), wdataFifoSize = 32, rdataFifoSize = 32)
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