Enable PMP register lock
This commit is contained in:
Samuel Lindemer
parent
fc2c8a7c37
commit
97fe279f7b
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@ -270,18 +270,18 @@ object CsrPluginConfig{
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marchid = 2,
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mimpid = 3,
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mhartid = 0,
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misaExtensionsInit = 0,
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misaAccess = CsrAccess.NONE,
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misaExtensionsInit = 0x103124, // RV32CFIMNU
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misaAccess = CsrAccess.READ_WRITE,
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mtvecAccess = CsrAccess.READ_WRITE,
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mtvecInit = mtvecInit,
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mepcAccess = CsrAccess.READ_WRITE,
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mscratchGen = true,
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mcauseAccess = CsrAccess.READ_ONLY,
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mbadaddrAccess = CsrAccess.READ_ONLY,
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mcycleAccess = CsrAccess.NONE,
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minstretAccess = CsrAccess.NONE,
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ucycleAccess = CsrAccess.NONE,
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uinstretAccess = CsrAccess.NONE,
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mcauseAccess = CsrAccess.READ_WRITE,
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mbadaddrAccess = CsrAccess.READ_WRITE,
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mcycleAccess = CsrAccess.READ_WRITE,
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minstretAccess = CsrAccess.READ_WRITE,
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ucycleAccess = CsrAccess.READ_ONLY,
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uinstretAccess = CsrAccess.READ_ONLY,
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wfiGenAsWait = true,
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ecallGen = true,
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userGen = true,
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@ -12,7 +12,7 @@ import spinal.lib._
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import scala.collection.mutable.ArrayBuffer
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/* Each 32-bit pmpcfg# register contains four 8-bit configuration sections.
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* These section numbers contain flags which apply to region defined by the
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* These section numbers contain flags which apply to regions defined by the
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* corresponding pmpaddr# register.
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*
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* 3 2 1
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@ -48,7 +48,7 @@ import scala.collection.mutable.ArrayBuffer
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* | address[33:2] | pmpaddr#
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* NAPOT: Each 32-bit pmpaddr# register defines the regionStart address and the size
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* NAPOT: Each 32-bit pmpaddr# register defines the region address and the size
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* of the pmp region. The number of concurrent 1s begging at the LSB indicates
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* the size of the region as a power of two (e.g. 0x...0 = 8-byte, 0x...1 =
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* 16-byte, 0x...11 = 32-byte, etc.).
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@ -63,39 +63,52 @@ import scala.collection.mutable.ArrayBuffer
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* register defines a 4-byte wide region.
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*/
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case class PmpRegister() extends Bundle {
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// CSR segments
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val x, w, r = Reg(Bool)
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val l = Reg(Bool) init(False)
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val a = Reg(UInt(2 bits)) init(0)
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val address = Reg(UInt(32 bits))
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// Computed region bounds
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val regionStart = UInt(32 bits)
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val regionEnd = UInt(32 bits)
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val valid = Bool
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case class PmpRegister() extends Area {
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// Addressing options
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def NA4 = 2
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def NAPOT = 3
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switch(a) {
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val csr = new Area {
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val r, w, x, l = RegInit(False)
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val a = Reg(UInt(2 bits)) init(0)
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val addr = Reg(UInt(32 bits))
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}
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val region = new Area {
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val r, w, x = Reg(Bool)
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val l = RegInit(False)
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val start = Reg(UInt(32 bits))
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val end = Reg(UInt(32 bits))
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val valid = RegInit(False)
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}
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// Internal CSR state is locked until reset if L-bit set
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when(~region.l) {
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region.r := csr.r
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region.w := csr.w
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region.x := csr.x
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region.l := csr.l
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switch(csr.a) {
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is(NA4) {
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regionStart := address |<< 2
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regionEnd := regionStart + 4
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valid := True
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val shifted = csr.addr |<< 2
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region.start := shifted
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region.end := shifted + 4
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region.valid := True
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}
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is(NAPOT) {
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val mask = address & ~(address + 1)
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regionStart := (address & ~mask) |<< 2
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regionEnd := regionStart + ((mask + 1) |<< 3)
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valid := True
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val mask = csr.addr & ~(csr.addr + 1)
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val shifted = (csr.addr & ~mask) |<< 2
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region.start := shifted
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region.end := shifted + ((mask + 1) |<< 3)
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region.valid := True
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}
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default {
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regionStart := 0
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regionEnd := 0
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valid := False
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region.start := 0
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region.end := 0
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region.valid := False
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}
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}
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}
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@ -130,20 +143,22 @@ class PmpPlugin(regions : Int, ioRange : UInt => Bool) extends Plugin[VexRiscv]
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// Instantiate pmpaddr0 ... pmpaddr# CSRs.
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for (n <- 0 until regions) {
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pmps += PmpRegister()
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csrService.rw(0x3B0 + n, pmps(n).address)
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csrService.rw(0x3B0 + n, pmps(n).csr.addr)
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}
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// Instantiate pmpcfg0 ... pmpcfg# CSRs.
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for (n <- 0 until (regions / 4)) {
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csrService.rw(0x3A0 + n,
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31 -> pmps((n * 4) + 3).l, 27 -> pmps((n * 4) + 3).a,
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26 -> pmps((n * 4) + 3).x, 25 -> pmps((n * 4) + 3).w, 24 -> pmps((n * 4) + 3).r,
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23 -> pmps((n * 4) + 2).l, 19 -> pmps((n * 4) + 2).a,
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18 -> pmps((n * 4) + 2).x, 17 -> pmps((n * 4) + 2).w, 16 -> pmps((n * 4) + 2).r,
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15 -> pmps((n * 4) + 1).l, 11 -> pmps((n * 4) + 1).a,
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10 -> pmps((n * 4) + 1).x, 9 -> pmps((n * 4) + 1).w, 8 -> pmps((n * 4) + 1).r,
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7 -> pmps((n * 4) ).l, 3 -> pmps((n * 4) ).a,
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2 -> pmps((n * 4) ).x, 1 -> pmps((n * 4) ).w, 0 -> pmps((n * 4) ).r
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31 -> pmps((n * 4) + 3).csr.l, 23 -> pmps((n * 4) + 2).csr.l,
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15 -> pmps((n * 4) + 1).csr.l, 7 -> pmps((n * 4) ).csr.l,
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27 -> pmps((n * 4) + 3).csr.a, 26 -> pmps((n * 4) + 3).csr.x,
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25 -> pmps((n * 4) + 3).csr.w, 24 -> pmps((n * 4) + 3).csr.r,
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19 -> pmps((n * 4) + 2).csr.a, 18 -> pmps((n * 4) + 2).csr.x,
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17 -> pmps((n * 4) + 2).csr.w, 16 -> pmps((n * 4) + 2).csr.r,
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11 -> pmps((n * 4) + 1).csr.a, 10 -> pmps((n * 4) + 1).csr.x,
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9 -> pmps((n * 4) + 1).csr.w, 8 -> pmps((n * 4) + 1).csr.r,
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3 -> pmps((n * 4) ).csr.a, 2 -> pmps((n * 4) ).csr.x,
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1 -> pmps((n * 4) ).csr.w, 0 -> pmps((n * 4) ).csr.r
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)
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}
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@ -154,10 +169,10 @@ class PmpPlugin(regions : Int, ioRange : UInt => Bool) extends Plugin[VexRiscv]
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port.bus.rsp.physicalAddress := address
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// Only the first matching PMP region is applied.
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val hits = pmps.map(pmp => pmp.valid &&
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pmp.regionStart <= address &&
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pmp.regionEnd > address &&
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(pmp.l || ~privilegeService.isMachine()))
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val hits = pmps.map(pmp => pmp.region.valid &&
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pmp.region.start <= address &&
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pmp.region.end > address &&
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(pmp.region.l || ~privilegeService.isMachine()))
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// M-mode has full access by default. All others have none by default.
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when(CountOne(hits) === 0) {
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@ -165,9 +180,9 @@ class PmpPlugin(regions : Int, ioRange : UInt => Bool) extends Plugin[VexRiscv]
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port.bus.rsp.allowWrite := privilegeService.isMachine()
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port.bus.rsp.allowExecute := privilegeService.isMachine()
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} otherwise {
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port.bus.rsp.allowRead := MuxOH(OHMasking.first(hits), pmps).r
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port.bus.rsp.allowWrite := MuxOH(OHMasking.first(hits), pmps).w
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port.bus.rsp.allowExecute := MuxOH(OHMasking.first(hits), pmps).x
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port.bus.rsp.allowRead := MuxOH(OHMasking.first(hits), pmps.map(_.region.r))
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port.bus.rsp.allowWrite := MuxOH(OHMasking.first(hits), pmps.map(_.region.w))
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port.bus.rsp.allowExecute := MuxOH(OHMasking.first(hits), pmps.map(_.region.x))
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}
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port.bus.rsp.isIoAccess := ioRange(port.bus.rsp.physicalAddress)
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