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VexRiscv
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Map all supervisor registers

This commit is contained in:
Dolu1990 2018-09-27 19:03:57 +02:00
parent acd1ca422a
commit 9a3510f63d
2 changed files with 34 additions and 0 deletions
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12
src/main/scala/vexriscv/Riscv.scala
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@ -131,6 +131,18 @@ object Riscv{
def MCYCLEH = 0xB80 // MRW Upper 32 bits of mcycle, RV32I only. def MCYCLEH = 0xB80 // MRW Upper 32 bits of mcycle, RV32I only.
def MINSTRETH = 0xB82 // MRW Upper 32 bits of minstret, RV32I only. def MINSTRETH = 0xB82 // MRW Upper 32 bits of minstret, RV32I only.
val SSTATUS = 0x100
val SIE = 0x104
val STVEC = 0x105
val SCOUNTEREN = 0x106
val SSCRATCH = 0x140
val SEPC = 0x141
val SCAUSE = 0x142
val SBADADDR = 0x143
val SIP = 0x144
val SATP = 0x180
def UCYCLE = 0xC00 // UR Machine ucycle counter. def UCYCLE = 0xC00 // UR Machine ucycle counter.
} }

22
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -51,6 +51,13 @@ case class CsrPluginConfig(
wfiGen : Boolean, wfiGen : Boolean,
ecallGen : Boolean, ecallGen : Boolean,
sscratchGen : Boolean = false, sscratchGen : Boolean = false,
stvecAccess : CsrAccess = CsrAccess.NONE,
sepcAccess : CsrAccess = CsrAccess.NONE,
scauseAccess : CsrAccess = CsrAccess.NONE,
sbadaddrAccess : CsrAccess = CsrAccess.NONE,
scycleAccess : CsrAccess = CsrAccess.NONE,
sinstretAccess : CsrAccess = CsrAccess.NONE,
satpAccess : CsrAccess = CsrAccess.NONE,
deterministicInteruptionEntry : Boolean = false //Only used for simulatation purposes deterministicInteruptionEntry : Boolean = false //Only used for simulatation purposes
){ ){
@ -380,6 +387,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
if(mhartid != null) READ_ONLY(CSR.MHARTID , U(mhartid )) if(mhartid != null) READ_ONLY(CSR.MHARTID , U(mhartid ))
//Machine CSR //Machine CSR
//TODO machine mode shadow supervisor
misaAccess(CSR.MISA, xlen-2 -> misa.base , 0 -> misa.extensions) misaAccess(CSR.MISA, xlen-2 -> misa.base , 0 -> misa.extensions)
READ_ONLY(CSR.MIP, 11 -> mip.MEIP, 7 -> mip.MTIP) READ_ONLY(CSR.MIP, 11 -> mip.MEIP, 7 -> mip.MTIP)
READ_WRITE(CSR.MIP, 3 -> mip.MSIP) READ_WRITE(CSR.MIP, 3 -> mip.MSIP)
@ -396,6 +404,20 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
minstretAccess(CSR.MINSTRET, minstret(31 downto 0)) minstretAccess(CSR.MINSTRET, minstret(31 downto 0))
minstretAccess(CSR.MINSTRETH, minstret(63 downto 32)) minstretAccess(CSR.MINSTRETH, minstret(63 downto 32))
//Supervisor CSR
READ_ONLY(CSR.SIP, 9 -> sip.SEIP, 5 -> sip.STIP)
READ_WRITE(CSR.SIP, 1 -> sip.SSIP)
READ_WRITE(CSR.SIE, 9 -> sie.SEIE, 5 -> sie.STIE, 1 -> sie.SSIE)
stvecAccess(CSR.STVEC, stvec)
sepcAccess(CSR.SEPC, sepc)
READ_WRITE(CSR.SSTATUS,9 -> sstatus.SPP, 5 -> sstatus.SPIE, 1 -> sstatus.SIE)
if(sscratchGen) READ_WRITE(CSR.SSCRATCH, sscratch)
scauseAccess(CSR.SCAUSE, xlen-1 -> scause.interrupt, 0 -> scause.exceptionCode)
sbadaddrAccess(CSR.SBADADDR, stval)
satpAccess(CSR.SATP, 31 -> satp.MODE, 22 -> satp.ASID, 0 -> satp.PPN)
//User CSR //User CSR
ucycleAccess(CSR.UCYCLE, mcycle(31 downto 0)) ucycleAccess(CSR.UCYCLE, mcycle(31 downto 0))