Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

IBusCachedPlugin twoStage config fix

This commit is contained in:
Charles Papon 2017-04-08 18:34:44 +02:00
parent e3b9e671ec
commit 9a4c35d7b6
1 changed files with 3 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala
View File

@ -370,6 +370,7 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
val valid = RegNext(lineLoader.waysWritePort.valid) val valid = RegNext(lineLoader.waysWritePort.valid)
val address = RegNext(lineLoader.request.addr(tagLineRange) @@ lineLoader.wordIndex @@ U"00") val address = RegNext(lineLoader.request.addr(tagLineRange) @@ lineLoader.wordIndex @@ U"00")
val data = RegNext(lineLoader.waysWritePort.data) val data = RegNext(lineLoader.waysWritePort.data)
val wasLoaded = RegNext(lineLoader.loadedWords)
} }
@ -385,8 +386,8 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{
fetchInstructionValid := True fetchInstructionValid := True
fetchInstructionValue := loadedWord.data fetchInstructionValue := loadedWord.data
} otherwise{ } otherwise{
fetchInstructionValid := waysHitValid fetchInstructionValid := waysHitValid || (loadedWord.address(tagLineRange) === io.cpu.fetch.address(tagLineRange) && loadedWord.wasLoaded(io.cpu.fetch.address(wordRange)))
fetchInstructionValue := waysHitWord fetchInstructionValue := waysHitWord //Not multi way (wasloaded)
} }