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VexRiscv
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riscv software model without RVC now trap on RVC instruction before pcWrite + 2

This commit is contained in:
Charles Papon 2019-04-13 10:40:53 +02:00
parent a12ca43284
commit 9ac1d3d59e
1 changed files with 3 additions and 0 deletions
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3
src/test/cpp/regression/main.cpp
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@ -957,6 +957,9 @@ public:
default: ilegalInstruction(); break; default: ilegalInstruction(); break;
} }
} else { } else {
#ifndef COMPRESSED
ilegalInstruction(); return;
#endif
switch((iBits(0, 2) << 3) + iBits(13, 3)){ switch((iBits(0, 2) << 3) + iBits(13, 3)){
case 0: rfWrite(i16_addr2, rf_sp + i16_addi4spn_imm); pcWrite(pc + 2); break; case 0: rfWrite(i16_addr2, rf_sp + i16_addi4spn_imm); pcWrite(pc + 2); break;
case 2: { case 2: {