Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fix FPU access trap on fs = 0 #297

This commit is contained in:
Dolu1990 2023-02-06 11:44:44 +01:00
parent fc9a9d25ed
commit 9acc5ddc1c
1 changed files with 6 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
src/main/scala/vexriscv/plugin/FpuPlugin.scala
View File

@ -233,10 +233,15 @@ class FpuPlugin(externalFpu : Boolean = false,
decode plug new Area{
import decode._
val trap = decode.input(FPU_ENABLE) && csr.fs === 0 && !stagesFromExecute.map(_.arbitration.isValid).orR
when(trap){
pipeline.service(classOf[DecoderService]).forceIllegal()
}
//Maybe it might be better to not fork before fire to avoid RF stall on commits
val forked = Reg(Bool) setWhen(port.cmd.fire) clearWhen(!arbitration.isStuck) init(False)
val hazard = csr.pendings.msb || csr.csrActive
val hazard = csr.pendings.msb || csr.csrActive || csr.fs === 0
arbitration.haltItself setWhen(arbitration.isValid && input(FPU_ENABLE) && hazard)
arbitration.haltItself setWhen(port.cmd.isStall)