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MachineCsr fix csr set/clear with zero 

MachineCsr pass external/timer interrupts test
This commit is contained in:
Charles Papon 2017-03-24 17:40:37 +01:00
parent 72d65841d2
commit 9bbf3ee3e7
4 changed files with 37 additions and 19 deletions
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10
src/main/scala/SpinalRiscv/Plugin/MachineCsr.scala
View File

@ -137,8 +137,8 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
pluginExceptionPort.valid := False
pluginExceptionPort.payload.assignDontCare()
timerInterrupt = in Bool()
externalInterrupt = in Bool()
timerInterrupt = in Bool() setName("timerInterrupt")
externalInterrupt = in Bool() setName("externalInterrupt")
}
@ -310,9 +310,9 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
val imm = IMM(input(INSTRUCTION))
val writeEnable = arbitration.isValid && !arbitration.isStuckByOthers && input(IS_CSR) &&
val writeEnable = arbitration.isValid && !arbitration.isStuckByOthers && !arbitration.removeIt && input(IS_CSR) &&
(!((input(INSTRUCTION)(14 downto 13) === "01" && input(INSTRUCTION)(rs1Range) === 0)
|| (input(INSTRUCTION)(14 downto 13) === "10" && imm.z === 0)))
|| (input(INSTRUCTION)(14 downto 13) === "11" && imm.z === 0)))
val writeSrc = input(INSTRUCTION)(14) ? imm.z.asBits.resized | input(SRC1)
@ -340,7 +340,7 @@ class MachineCsr(config : MachineCsrConfig) extends Plugin[VexRiscv] with Except
}
for (element <- jobs) element match {
case element: CsrRead => readData(element.bitOffset, element.that.getBitsWidth bits) := element.that.asBits
case element: CsrRead if element.that.getBitsWidth != 0 => readData(element.bitOffset, element.that.getBitsWidth bits) := element.that.asBits
case _ =>
}
}

2
src/main/scala/SpinalRiscv/TopLevel.scala
View File

@ -36,7 +36,7 @@ object TopLevel {
mvendorid = 11,
marchid = 22,
mimpid = 33,
mhartid = 44,
mhartid = 0,
misaExtensionsInit = 66,
misaAccess = READ_WRITE,
mtvecAccess = READ_WRITE,

19
src/test/cpp/testA/main.cpp
View File

@ -199,6 +199,10 @@ public:
top->eval(); currentTime = 3;
top->reset = 1;
top->eval();
#ifdef CSR
top->timerInterrupt = 1;
top->externalInterrupt = 1;
#endif
dump(0);
top->reset = 0;
top->eval(); currentTime = 2;
@ -384,7 +388,11 @@ public:
}
virtual void postReset() {
// #ifdef CSR
// top->VexRiscv->prefetch_PcManagerSimplePlugin_pcReg = 0x80000000u;
// #else
top->VexRiscv->prefetch_PcManagerSimplePlugin_pcReg = 0x800000bcu;
// #endif
}
virtual void checks(){
@ -540,6 +548,12 @@ int main(int argc, char **argv, char **env) {
redo(REDO,RiscvTest(name).run();)
}
#endif
#ifdef CSR
uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3,0x80000007u, 4,0x8000000bu, 5};
redo(REDO,TestX28("machineCsr",machineCsrRef, sizeof(machineCsrRef)/4).run(2e3);)
#endif
#ifdef DHRYSTONE
Dhrystone("dhrystoneO3",true,true).run(1e6);
Dhrystone("dhrystoneO3M",true,true).run(0.8e6);
@ -547,10 +561,7 @@ int main(int argc, char **argv, char **env) {
// Dhrystone("dhrystoneO3ML",false,false).run(8e6);
// Dhrystone("dhrystoneO3MLL",false,false).run(80e6);
#endif
#ifdef CSR
uint32_t machineCsrRef[] = {1,11, 2,0x80000003u, 3};
TestX28("machineCsr",machineCsrRef, sizeof(machineCsrRef)/4).run(2e3);
#endif
}

25
src/test/resources/hex/machineCsr.hex
View File

@ -1,14 +1,21 @@
:100000006F00000513000000130000001300000043
:100000006F00000713000000130000001300000041
:100010001300000013000000130000001300000094
:10002000732E2034930EB0006398CE01F32E10345B
:10003000938E4E0073901E34B70E0080938E3E0058
:100040006396CE01930E800073B04E34730020305F
:10005000130E100073000000130E200093028000A6
:1000600073A00230930280007390423093028000AC
:1000700073A04234130000001300000013000000BE
:100080001300000013000000130000001300000024
:100090001300000013000000130000001300000014
:0800A00013000000130E3000F4
:100040006396CE01930E800073B04E34B70E0080DD
:10005000938E7E006394CE0173504030B70E0080C3
:10006000938EBE006394CE017350403073002030F5
:10007000130E100073000000130E20009302800086
:1000800073A002309302800073904230930280008C
:1000900073A042341300000013000000130000009E
:1000A0001300000013000000130000001300000004
:1000B00013000000130000001300000013000000F4
:1000C00013000000130E30009302000873904230BA
:1000D00013000000130000001300000013000000D4
:1000E000130000001300000013000000130E400076
:1000F000B712000093820280739042301300000018
:1001000013000000130000001300000013000000A3
:0C0110001300000013000000130E50004C
:020000044000BA
:1000000013050000678000001305000067800000F2
:1000100097020000678082FF1305000067800000E0
@ -3182,5 +3189,5 @@
:10C6100008C6004008C6004010C6004010C60040D2
:10C6200018C6004018C6004080BD004080BD0040D4
:10C6300001000000FFFFFFFF00000200C88900406A
:0400000300000050A9
:040000030000007089
:00000001FF