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VexRiscv
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A FPGA friendly 32 bit RISC-V CPU implementation
36 Commits 39 Branches 2 Tags 15 MiB
Assembly 62%
Scala 26.9%
C++ 4.7%
C 3.8%
Tcl 1.2%
Other 1.3%
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Charles Papon 9bbf3ee3e7 MachineCsr fix csr set/clear with zero 
MachineCsr pass external/timer interrupts test
 		2017-03-24 17:40:37 +01:00
project boot 2017-03-08 22:17:48 +01:00
src MachineCsr fix csr set/clear with zero 2017-03-24 17:40:37 +01:00
.gitignore Add self checked dhrystone test 2017-03-18 12:32:14 +01:00
README.md boot 2017-03-08 22:17:48 +01:00
backup boot 2017-03-08 22:17:48 +01:00
build.sbt WIP 2017-03-11 00:34:49 +01:00

README.md

WIP