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updated related to JtagInstructionWrapper.ignoreWidth

This commit is contained in:
Dolu1990 2022-01-14 09:59:22 +01:00
parent b8e904e43f
commit 9c34a1fd2e
5 changed files with 13 additions and 10 deletions
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2
src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
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@ -113,7 +113,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
withDebug.get match { withDebug.get match {
case DEBUG_JTAG => jtag <> plugin.io.bus.fromJtag() case DEBUG_JTAG => jtag <> plugin.io.bus.fromJtag()
case DEBUG_JTAG_CTRL => jtagInstructionCtrl <> plugin.io.bus.fromJtagInstructionCtrl(jtagClockDomain) case DEBUG_JTAG_CTRL => jtagInstructionCtrl <> plugin.io.bus.fromJtagInstructionCtrl(jtagClockDomain, 0)
case DEBUG_BUS => debugBus <> plugin.io.bus case DEBUG_BUS => debugBus <> plugin.io.bus
case DEBUG_BMB => debugBmb >> plugin.io.bus.fromBmb() case DEBUG_BMB => debugBmb >> plugin.io.bus.fromBmb()
} }

3
src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
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@ -26,6 +26,7 @@ import spinal.lib.generator._
import vexriscv.ip.fpu.FpuParameter import vexriscv.ip.fpu.FpuParameter
case class VexRiscvSmpClusterParameter(cpuConfigs : Seq[VexRiscvConfig], case class VexRiscvSmpClusterParameter(cpuConfigs : Seq[VexRiscvConfig],
jtagHeaderIgnoreWidth : Int,
withExclusiveAndInvalidation : Boolean, withExclusiveAndInvalidation : Boolean,
forcePeripheralWidth : Boolean = true, forcePeripheralWidth : Boolean = true,
outOfOrderDecoder : Boolean = true, outOfOrderDecoder : Boolean = true,
@ -51,7 +52,7 @@ class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Area with
implicit val interconnect = BmbInterconnectGenerator() implicit val interconnect = BmbInterconnectGenerator()
val debugBridge = debugCd.outputClockDomain on JtagInstructionDebuggerGenerator() val debugBridge = debugCd.outputClockDomain on JtagInstructionDebuggerGenerator(p.jtagHeaderIgnoreWidth)
debugBridge.jtagClockDomain.load(ClockDomain.external("jtag", withReset = false)) debugBridge.jtagClockDomain.load(ClockDomain.external("jtag", withReset = false))
val debugPort = Handle(debugBridge.logic.jtagBridge.io.ctrl.toIo) val debugPort = Handle(debugBridge.logic.jtagBridge.io.ctrl.toIo)

6
src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
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@ -175,7 +175,8 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
withExclusiveAndInvalidation = coherency, withExclusiveAndInvalidation = coherency,
forcePeripheralWidth = !wishboneMemory, forcePeripheralWidth = !wishboneMemory,
outOfOrderDecoder = outOfOrderDecoder, outOfOrderDecoder = outOfOrderDecoder,
fpu = fpu fpu = fpu,
jtagHeaderIgnoreWidth = 0
), ),
liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = liteDramWidth), liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = liteDramWidth),
liteDramMapping = SizeMapping(0x40000000l, 0x40000000l), liteDramMapping = SizeMapping(0x40000000l, 0x40000000l),
@ -250,7 +251,8 @@ object VexRiscvLitexSmpClusterOpenSbi extends App{
resetVector = 0x80000000l resetVector = 0x80000000l
) )
}, },
withExclusiveAndInvalidation = true withExclusiveAndInvalidation = true,
jtagHeaderIgnoreWidth = 0
), ),
liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128), liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128),
liteDramMapping = SizeMapping(0x80000000l, 0x70000000l), liteDramMapping = SizeMapping(0x80000000l, 0x70000000l),

4
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
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@ -567,8 +567,8 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
} }
} }
if(!earlyInjection && !emitCmdInMemoryStage && config.withWriteBackStage) // if(!earlyInjection && !emitCmdInMemoryStage && config.withWriteBackStage)
assert(!(arbitration.isValid && input(MEMORY_ENABLE) && !input(MEMORY_STORE) && arbitration.isStuck),"DBusSimplePlugin doesn't allow writeback stage stall when read happend") // assert(!(arbitration.isValid && input(MEMORY_ENABLE) && !input(MEMORY_STORE) && arbitration.isStuck),"DBusSimplePlugin doesn't allow writeback stage stall when read happend")
//formal //formal
insert(FORMAL_MEM_RDATA) := input(MEMORY_READ_DATA) insert(FORMAL_MEM_RDATA) := input(MEMORY_READ_DATA)

8
src/main/scala/vexriscv/plugin/DebugPlugin.scala
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@ -137,13 +137,13 @@ case class DebugExtensionBus() extends Bundle with IMasterSlave{
jtagBridge.io.jtag jtagBridge.io.jtag
} }
def fromJtagInstructionCtrl(jtagClockDomain : ClockDomain): JtagTapInstructionCtrl ={ def fromJtagInstructionCtrl(jtagClockDomain : ClockDomain, jtagHeaderIgnoreWidth : Int): JtagTapInstructionCtrl ={
val jtagConfig = SystemDebuggerConfig( val jtagConfig = SystemDebuggerConfig(
memAddressWidth = 32, memAddressWidth = 32,
memDataWidth = 32, memDataWidth = 32,
remoteCmdWidth = 1 remoteCmdWidth = 1
) )
val jtagBridge = new JtagBridgeNoTap(jtagConfig, jtagClockDomain) val jtagBridge = new JtagBridgeNoTap(jtagConfig, jtagClockDomain, jtagHeaderIgnoreWidth)
val debugger = new SystemDebugger(jtagConfig) val debugger = new SystemDebugger(jtagConfig)
debugger.io.remote <> jtagBridge.io.remote debugger.io.remote <> jtagBridge.io.remote
debugger.io.mem <> this.from(jtagConfig) debugger.io.mem <> this.from(jtagConfig)
@ -151,13 +151,13 @@ case class DebugExtensionBus() extends Bundle with IMasterSlave{
jtagBridge.io.ctrl jtagBridge.io.ctrl
} }
def fromBscane2(usedId : Int): Unit ={ def fromBscane2(usedId : Int, jtagHeaderIgnoreWidth : Int): Unit ={
val jtagConfig = SystemDebuggerConfig() val jtagConfig = SystemDebuggerConfig()
val bscane2 = BSCANE2(usedId) val bscane2 = BSCANE2(usedId)
val jtagClockDomain = ClockDomain(bscane2.TCK) val jtagClockDomain = ClockDomain(bscane2.TCK)
val jtagBridge = new JtagBridgeNoTap(jtagConfig, jtagClockDomain) val jtagBridge = new JtagBridgeNoTap(jtagConfig, jtagClockDomain, jtagHeaderIgnoreWidth)
jtagBridge.io.ctrl << bscane2.toJtagTapInstructionCtrl() jtagBridge.io.ctrl << bscane2.toJtagTapInstructionCtrl()
val debugger = new SystemDebugger(jtagConfig) val debugger = new SystemDebugger(jtagConfig)