Package refractoring VexRiscv -> vexriscv Plugin -> plugin

README.md

@@ -24,7 +24,7 @@ This repository host an RISC-V implementation written in SpinalHDL. There is som
 - Optional MUL/DIV extension
 - Optional instruction and data caches
 - Optional MMU
-- Optional debug extension allowing GDB debugging via an openOCD JTAG connection
+- Optional debug extension allowing eclipse debugging via an GDB >> openOCD >> JTAG connection
 - Optional interrupts and exception handling with the Machine and the User mode from the riscv-privileged-v1.9.1 spec.
 - Two implementation of shift instructions, Single cycle / shiftNumber cycles
 - Each stage could have bypass or interlock hazard logic
@@ -40,7 +40,7 @@ The hardware description of this CPU is done by using an very software oriented
 ## Area usage and maximal frequency 
 
 The following number where obtains by synthesis the CPU as toplevel without any specific synthesis option to save area or to get better maximal frequency (neutral).
-The used CPU corresponding configuration can be find in src/scala/VexRiscv/demo.
+The used CPU corresponding configuration can be find in src/scala/vexriscv/demo.
 
 ```
 VexRiscv smallest (RV32I, 0.47 DMIPS/Mhz, no datapath bypass, no interrupt) ->
@@ -110,8 +110,8 @@ sudo make install
 
 ## CPU generation
 You can find two example of CPU instantiation in :
-- src/main/scala/VexRiscv/GenFull.scala
-- src/main/scala/VexRiscv/GenSmallest.scala
+- src/main/scala/vexriscv/GenFull.scala
+- src/main/scala/vexriscv/GenSmallest.scala
 
 To generate the corresponding RTL as a VexRiscv.v file, run (it could take time the first time you run it):
 
@@ -119,10 +119,10 @@ NOTE :
 The VexRiscv could need the unreleased master-head of SpinalHDL. If it fail to compile, just get the SpinalHDL repository and do a "sbt publish-local" in it.
 
 ```sh
-sbt "run-main VexRiscv.demo.GenFull"
+sbt "run-main vexriscv.demo.GenFull"
 
 # or
-sbt "run-main VexRiscv.demo.GenSmallest"
+sbt "run-main vexriscv.demo.GenSmallest"
 ```
 
 ## Regression tests
@@ -144,7 +144,7 @@ Then you can use the https://github.com/SpinalHDL/openocd_riscv tool to create a
 
 ```sh
 #in the VexRiscv repository, to run the simulation on which one OpenOCD can connect itself =>
-sbt "run-main VexRiscv.demo.GenFull"
+sbt "run-main vexriscv.demo.GenFull"
 cd src/test/cpp/regression
 make run DEBUG_PLUGIN_EXTERNAL=yes
 
@@ -165,7 +165,7 @@ continue
 You can use the eclipse + zilin embedded CDT plugin to do it (http://opensource.zylin.com/embeddedcdt.html). Tested with Helios Service Release 2 and the corresponding zylin plugin.
 
 ## Briey SoC
-As a demonstrator, a SoC named Briey is implemented in src/main/scala/VexRiscv/demo/Briey.scala. This SoC is very similar to the Pinsec one  :
+As a demonstrator, a SoC named Briey is implemented in src/main/scala/vexriscv/demo/Briey.scala. This SoC is very similar to the Pinsec one  :
 
 <img src="http://cdn.rawgit.com/SpinalHDL/SpinalDoc/dd17971aa549ccb99168afd55aad274bbdff1e88/asset/picture/pinsec_hardware.svg"   align="middle" width="300">
 
@@ -173,7 +173,7 @@ As a demonstrator, a SoC named Briey is implemented in src/main/scala/VexRiscv/d
 To generate the Briey SoC Hardware :
 
 ```sh
-sbt "run-main VexRiscv.demo.Briey"
+sbt "run-main vexriscv.demo.Briey"
 ```
 
 To run the verilator simulation of the Briey SoC which can be then connected to OpenOCD/GDB, first get those dependencies :
@@ -240,9 +240,12 @@ echo -e "\\nRISC-V Toolchain installation completed!"
 
 ## CPU parametrization and instantiation example
 
-You can find many example of different config in the https://github.com/SpinalHDL/VexRiscv/tree/master/src/main/scala/VexRiscv/demo folder. There is one :
+You can find many example of different config in the https://github.com/SpinalHDL/VexRiscv/tree/master/src/main/scala/vexriscv/demo folder. There is one :
 
 ```scala
+import vexriscv._
+import vexriscv.plugin._
+
 //Instanciate one VexRiscv
 val cpu = new VexRiscv(
   //Provide a configuration instance
@@ -297,8 +300,8 @@ There is an example of an simple plugin which add an simple SIMD_ADD instruction
 
 ```scala
 import spinal.core._
-import VexRiscv.Plugin.Plugin
-import VexRiscv.{Stageable, DecoderService, VexRiscv}
+import vexriscv.plugin.Plugin
+import vexriscv.{Stageable, DecoderService, VexRiscv}
 
 //This plugin example will add a new instruction named SIMD_ADD which do the following :
 //

src/main/scala/vexriscv/Pipeline.scala

@@ -1,6 +1,6 @@
-package VexRiscv
+package vexriscv
 
-import VexRiscv.Plugin._
+import vexriscv.plugin._
 import spinal.core._
 import spinal.lib._
 

src/main/scala/vexriscv/Riscv.scala

@@ -1,4 +1,4 @@
-package VexRiscv
+package vexriscv
 
 import spinal.core._
 

src/main/scala/vexriscv/Services.scala

@@ -1,4 +1,4 @@
-package VexRiscv
+package vexriscv
 
 import java.util
 

src/main/scala/vexriscv/Stage.scala

@@ -1,4 +1,4 @@
-package VexRiscv
+package vexriscv
 
 import spinal.core._
 import spinal.lib._

src/main/scala/vexriscv/TestsWorkspace.scala

@@ -16,13 +16,13 @@
  * License along with this library.
  */
 
-package VexRiscv
+package vexriscv
 
-import VexRiscv.Plugin._
-import VexRiscv.demo.SimdAddPlugin
+import vexriscv.plugin._
+import vexriscv.demo.SimdAddPlugin
 import spinal.core._
 import spinal.lib._
-import VexRiscv.ip._
+import vexriscv.ip._
 import spinal.lib.bus.avalon.AvalonMM
 import spinal.lib.eda.altera.{InterruptReceiverTag, ResetEmitterTag}
 
@@ -90,7 +90,7 @@ object TestsWorkspace {
             catchIllegalInstruction = true
           ),
           new RegFilePlugin(
-            regFileReadyKind = Plugin.SYNC,
+            regFileReadyKind = plugin.SYNC,
             zeroBoot = true
           ),
           new IntAluPlugin,
@@ -140,7 +140,7 @@ object TestsWorkspace {
             catchIllegalInstruction = false
           ),
           new RegFilePlugin(
-            regFileReadyKind = Plugin.ASYNC,
+            regFileReadyKind = plugin.ASYNC,
             zeroBoot = false
           ),
           new IntAluPlugin,
@@ -191,7 +191,7 @@ object TestsWorkspace {
             catchIllegalInstruction = true
           ),
           new RegFilePlugin(
-            regFileReadyKind = Plugin.SYNC,
+            regFileReadyKind = plugin.SYNC,
             zeroBoot = true
           ),
           new IntAluPlugin,

src/main/scala/vexriscv/VexRiscv.scala

@@ -1,6 +1,6 @@
-package VexRiscv
+package vexriscv
 
-import VexRiscv.Plugin._
+import vexriscv.plugin._
 import spinal.core._
 
 case class VexRiscvConfig(plugins : Seq[Plugin[VexRiscv]]){

src/main/scala/vexriscv/demo/Briey.scala

@@ -1,9 +1,9 @@
-package VexRiscv.demo
+package vexriscv.demo
 
 
-import VexRiscv.Plugin._
-import VexRiscv._
-import VexRiscv.ip.{DataCacheConfig, InstructionCacheConfig}
+import vexriscv.plugin._
+import vexriscv._
+import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
 import spinal.core._
 import spinal.lib._
 import spinal.lib.bus.amba3.apb._
@@ -231,7 +231,7 @@ class Briey(config: BrieyConfig) extends Component{
             catchIllegalInstruction = true
           ),
           new RegFilePlugin(
-            regFileReadyKind = Plugin.SYNC,
+            regFileReadyKind = plugin.SYNC,
             zeroBoot = false
           ),
           new IntAluPlugin,
@@ -367,28 +367,12 @@ class Briey(config: BrieyConfig) extends Component{
       )
     )
 
-    //Add JTAG
-    val jtagConfig = SystemDebuggerConfig(
-      memAddressWidth = 32,
-      memDataWidth    = 32,
-      remoteCmdWidth  = 1
-    )
-    val jtagBridge = new JtagBridge(jtagConfig)
-    val debugger = new SystemDebugger(jtagConfig)
-    debugger.io.remote <> jtagBridge.io.remote
-    debugger.io.mem.cmd.valid           <> core.debugBus.cmd.valid
-    debugger.io.mem.cmd.ready           <> core.debugBus.cmd.ready
-    debugger.io.mem.cmd.wr              <> core.debugBus.cmd.wr
-    debugger.io.mem.cmd.address.resized <> core.debugBus.cmd.address
-    debugger.io.mem.cmd.data            <> core.debugBus.cmd.data
-    debugger.io.mem.rsp.valid           <> RegNext(core.debugBus.cmd.fire).init(False)
-    debugger.io.mem.rsp.payload         <> core.debugBus.rsp.data
+    io.jtag <> core.debugBus.fromJtag()
   }
 
   io.gpioA          <> axi.gpioACtrl.io.gpio
   io.gpioB          <> axi.gpioBCtrl.io.gpio
   io.timerExternal  <> axi.timerCtrl.io.external
-  io.jtag           <> axi.jtagBridge.io.jtag
   io.uart           <> axi.uartCtrl.io.uart
   io.sdram          <> axi.sdramCtrl.io.sdram
   io.vga            <> axi.vgaCtrl.io.vga

src/main/scala/vexriscv/demo/CustomInstruction.scala

@@ -1,8 +1,8 @@
-package VexRiscv.demo
+package vexriscv.demo
 
 import spinal.core._
-import VexRiscv.Plugin.Plugin
-import VexRiscv.{Stageable, DecoderService, VexRiscv}
+import vexriscv.plugin.Plugin
+import vexriscv.{Stageable, DecoderService, VexRiscv}
 
 //This plugin example will add a new instruction named SIMD_ADD which do the following :
 //

src/main/scala/vexriscv/demo/GenFull.scala

@@ -1,8 +1,8 @@
-package VexRiscv.demo
+package vexriscv.demo
 
-import VexRiscv.Plugin._
-import VexRiscv.ip.{DataCacheConfig, InstructionCacheConfig}
-import VexRiscv.{Plugin, VexRiscv, VexRiscvConfig}
+import vexriscv.plugin._
+import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
+import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
 import spinal.core._
 
 /**
@@ -62,7 +62,7 @@ object GenFull extends App{
           catchIllegalInstruction = true
         ),
         new RegFilePlugin(
-          regFileReadyKind = Plugin.SYNC,
+          regFileReadyKind = plugin.SYNC,
           zeroBoot = true
         ),
         new IntAluPlugin,

src/main/scala/vexriscv/demo/GenFullNoMmu.scala

@@ -1,8 +1,8 @@
-package VexRiscv.demo
+package vexriscv.demo
 
-import VexRiscv.Plugin._
-import VexRiscv.ip.{DataCacheConfig, InstructionCacheConfig}
-import VexRiscv.{Plugin, VexRiscv, VexRiscvConfig}
+import vexriscv.plugin._
+import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
+import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
 import spinal.core._
 
 /**
@@ -53,7 +53,7 @@ object GenFullNoMmu extends App{
           catchIllegalInstruction = true
         ),
         new RegFilePlugin(
-          regFileReadyKind = Plugin.SYNC,
+          regFileReadyKind = plugin.SYNC,
           zeroBoot = true
         ),
         new IntAluPlugin,

src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala

@@ -1,8 +1,8 @@
-package VexRiscv.demo
+package vexriscv.demo
 
-import VexRiscv.Plugin._
-import VexRiscv.ip.{DataCacheConfig, InstructionCacheConfig}
-import VexRiscv.{Plugin, VexRiscv, VexRiscvConfig}
+import vexriscv.plugin._
+import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
+import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
 import spinal.core._
 
 /**
@@ -28,7 +28,7 @@ object GenFullNoMmuNoCache extends App{
           catchIllegalInstruction = true
         ),
         new RegFilePlugin(
-          regFileReadyKind = Plugin.SYNC,
+          regFileReadyKind = plugin.SYNC,
           zeroBoot = true
         ),
         new IntAluPlugin,

src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala

@@ -1,7 +1,7 @@
-package VexRiscv.demo
+package vexriscv.demo
 
-import VexRiscv.Plugin._
-import VexRiscv.{Plugin, VexRiscv, VexRiscvConfig}
+import vexriscv.plugin._
+import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
 import spinal.core._
 
 /**
@@ -28,7 +28,7 @@ object GenSmallAndProductive extends App{
           catchIllegalInstruction = false
         ),
         new RegFilePlugin(
-          regFileReadyKind = Plugin.SYNC,
+          regFileReadyKind = plugin.SYNC,
           zeroBoot = true
         ),
         new IntAluPlugin,

src/main/scala/vexriscv/demo/GenSmallest.scala

@@ -1,7 +1,7 @@
-package VexRiscv.demo
+package vexriscv.demo
 
-import VexRiscv.Plugin._
-import VexRiscv.{Plugin, VexRiscv, VexRiscvConfig}
+import vexriscv.plugin._
+import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
 import spinal.core._
 
 /**
@@ -28,7 +28,7 @@ object GenSmallest extends App{
           catchIllegalInstruction = false
         ),
         new RegFilePlugin(
-          regFileReadyKind = Plugin.SYNC,
+          regFileReadyKind = plugin.SYNC,
           zeroBoot = true
         ),
         new IntAluPlugin,

src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala

@@ -1,7 +1,7 @@
-package VexRiscv.demo
+package vexriscv.demo
 
-import VexRiscv.Plugin._
-import VexRiscv.{Plugin, VexRiscv, VexRiscvConfig}
+import vexriscv.plugin._
+import vexriscv.{plugin, VexRiscv, VexRiscvConfig}
 import spinal.core._
 
 /**
@@ -27,7 +27,7 @@ object GenSmallestNoCsr extends App{
           catchIllegalInstruction = false
         ),
         new RegFilePlugin(
-          regFileReadyKind = Plugin.SYNC,
+          regFileReadyKind = plugin.SYNC,
           zeroBoot = true
         ),
         new IntAluPlugin,

src/main/scala/vexriscv/demo/SynthesisBench.scala

@@ -1,4 +1,4 @@
-package VexRiscv.demo
+package vexriscv.demo
 
 import spinal.core.SpinalVerilog
 import spinal.lib.eda.bench.{XilinxStdTargets, Bench, AlteraStdTargets, Rtl}

src/main/scala/vexriscv/demo/VexRiscvAvalon.scala

@@ -1,8 +1,8 @@
-package VexRiscv.demo
+package vexriscv.demo
 
-import VexRiscv.Plugin._
-import VexRiscv.{VexRiscv, Plugin, VexRiscvConfig}
-import VexRiscv.ip.{DataCacheConfig, InstructionCacheConfig}
+import vexriscv.plugin._
+import vexriscv.{VexRiscv, plugin, VexRiscvConfig}
+import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
 import spinal.core._
 import spinal.lib._
 import spinal.lib.bus.amba3.apb.Apb3
@@ -71,7 +71,7 @@ object VexRiscvAvalon{
             catchIllegalInstruction = true
           ),
           new RegFilePlugin(
-            regFileReadyKind = Plugin.SYNC,
+            regFileReadyKind = plugin.SYNC,
             zeroBoot = false
           ),
           new IntAluPlugin,

src/main/scala/vexriscv/ip/DataCache.scala

@@ -1,6 +1,6 @@
-package VexRiscv.ip
+package vexriscv.ip
 
-import VexRiscv._
+import vexriscv._
 import spinal.core._
 import spinal.lib._
 import spinal.lib.bus.amba4.axi.{Axi4Shared, Axi4Config}

src/main/scala/vexriscv/ip/InstructionCache.scala

@@ -1,6 +1,6 @@
-package VexRiscv.ip
+package vexriscv.ip
 
-import VexRiscv._
+import vexriscv._
 import spinal.core._
 import spinal.lib._
 import spinal.lib.bus.amba4.axi.{Axi4ReadOnly, Axi4Config}

src/main/scala/vexriscv/plugin/BranchPlugin.scala

@@ -1,7 +1,7 @@
-package VexRiscv.Plugin
+package vexriscv.plugin
 
-import VexRiscv.Riscv._
-import VexRiscv._
+import vexriscv.Riscv._
+import vexriscv._
 import spinal.core._
 import spinal.lib._
 

src/main/scala/vexriscv/plugin/CsrPlugin.scala

@@ -1,9 +1,9 @@
-package VexRiscv.Plugin
+package vexriscv.plugin
 
 import spinal.core._
 import spinal.lib._
-import VexRiscv._
-import VexRiscv.Riscv._
+import vexriscv._
+import vexriscv.Riscv._
 
 import scala.collection.mutable.ArrayBuffer
 import scala.collection.mutable

src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala

@@ -1,7 +1,7 @@
-package VexRiscv.Plugin
+package vexriscv.plugin
 
-import VexRiscv.ip._
-import VexRiscv._
+import vexriscv.ip._
+import vexriscv._
 import spinal.core._
 import spinal.lib._
 

src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala

@@ -1,6 +1,6 @@
-package VexRiscv.Plugin
+package vexriscv.plugin
 
-import VexRiscv._
+import vexriscv._
 import spinal.core._
 import spinal.lib._
 import spinal.lib.bus.amba4.axi._

src/main/scala/vexriscv/plugin/DebugPlugin.scala

@@ -1,8 +1,10 @@
-package VexRiscv.Plugin
+package vexriscv.plugin
 
-import VexRiscv.Plugin.IntAluPlugin.{AluCtrlEnum, ALU_CTRL}
-import VexRiscv._
-import VexRiscv.ip._
+import spinal.lib.com.jtag.Jtag
+import spinal.lib.system.debugger.{SystemDebugger, JtagBridge, SystemDebuggerConfig}
+import vexriscv.plugin.IntAluPlugin.{AluCtrlEnum, ALU_CTRL}
+import vexriscv._
+import vexriscv.ip._
 import spinal.core._
 import spinal.lib._
 import spinal.lib.bus.amba3.apb.{Apb3Config, Apb3}
@@ -58,6 +60,26 @@ case class DebugExtensionBus() extends Bundle with IMasterSlave{
 
     bus
   }
+
+  def fromJtag(): Jtag ={
+    val jtagConfig = SystemDebuggerConfig(
+      memAddressWidth = 32,
+      memDataWidth    = 32,
+      remoteCmdWidth  = 1
+    )
+    val jtagBridge = new JtagBridge(jtagConfig)
+    val debugger = new SystemDebugger(jtagConfig)
+    debugger.io.remote <> jtagBridge.io.remote
+    debugger.io.mem.cmd.valid           <> cmd.valid
+    debugger.io.mem.cmd.ready           <> cmd.ready
+    debugger.io.mem.cmd.wr              <> cmd.wr
+    debugger.io.mem.cmd.address.resized <> cmd.address
+    debugger.io.mem.cmd.data            <> cmd.data
+    debugger.io.mem.rsp.valid           <> RegNext(cmd.fire).init(False)
+    debugger.io.mem.rsp.payload         <> rsp.data
+
+    jtagBridge.io.jtag
+  }
 }
 
 case class DebugExtensionIo() extends Bundle with IMasterSlave{

src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala

@@ -1,6 +1,6 @@
-package VexRiscv.Plugin
+package vexriscv.plugin
 
-import VexRiscv._
+import vexriscv._
 import spinal.core._
 import spinal.lib._
 

src/main/scala/vexriscv/plugin/DivPlugin.scala

@@ -1,6 +1,6 @@
-package VexRiscv.Plugin
+package vexriscv.plugin
 
-import VexRiscv.{VexRiscv, _}
+import vexriscv.{VexRiscv, _}
 import spinal.core._
 import spinal.lib.math.MixedDivider
 

src/main/scala/vexriscv/plugin/HazardPessimisticPlugin.scala

@@ -1,6 +1,6 @@
-package VexRiscv.Plugin
+package vexriscv.plugin
 
-import VexRiscv._
+import vexriscv._
 import spinal.core._
 import spinal.lib._
 

src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala

@@ -1,6 +1,6 @@
-package VexRiscv.Plugin
+package vexriscv.plugin
 
-import VexRiscv._
+import vexriscv._
 import spinal.core._
 import spinal.lib._
 

src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala

@@ -1,7 +1,7 @@
-package VexRiscv.Plugin
+package vexriscv.plugin
 
-import VexRiscv._
-import VexRiscv.ip._
+import vexriscv._
+import vexriscv.ip._
 import spinal.core._
 import spinal.lib._
 

src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala

@@ -1,6 +1,6 @@
-package VexRiscv.Plugin
+package vexriscv.plugin
 
-import VexRiscv.{Stageable, ExceptionService, ExceptionCause, VexRiscv}
+import vexriscv.{Stageable, ExceptionService, ExceptionCause, VexRiscv}
 import spinal.core._
 import spinal.lib._
 import spinal.lib.bus.amba4.axi._

src/main/scala/vexriscv/plugin/IntAluPlugin.scala

@@ -1,6 +1,6 @@
-package VexRiscv.Plugin
+package vexriscv.plugin
 
-import VexRiscv._
+import vexriscv._
 import spinal.core._
 object IntAluPlugin{
   object AluBitwiseCtrlEnum extends SpinalEnum(binarySequential){

src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala

@@ -1,6 +1,6 @@
-package VexRiscv.Plugin
+package vexriscv.plugin
 
-import VexRiscv.{VexRiscv, _}
+import vexriscv.{VexRiscv, _}
 import spinal.core._
 import spinal.lib._
 

src/main/scala/vexriscv/plugin/MulPlugin.scala

@@ -1,6 +1,6 @@
-package VexRiscv.Plugin
-import VexRiscv._
-import VexRiscv.VexRiscv
+package vexriscv.plugin
+import vexriscv._
+import vexriscv.VexRiscv
 import spinal.core._
 
 class MulPlugin extends Plugin[VexRiscv]{

src/main/scala/vexriscv/plugin/PcManagerSimplePlugin.scala

@@ -1,6 +1,6 @@
-package VexRiscv.Plugin
+package vexriscv.plugin
 
-import VexRiscv._
+import vexriscv._
 import spinal.core._
 import spinal.lib._
 

src/main/scala/vexriscv/plugin/Plugin.scala

@@ -1,6 +1,6 @@
-package VexRiscv.Plugin
+package vexriscv.plugin
 
-import VexRiscv.{Pipeline, Stage}
+import vexriscv.{Pipeline, Stage}
 import spinal.core.Area
 
 /**

src/main/scala/vexriscv/plugin/RegFilePlugin.scala

@@ -1,6 +1,6 @@
-package VexRiscv.Plugin
+package vexriscv.plugin
 
-import VexRiscv._
+import vexriscv._
 import spinal.core._
 import spinal.lib._
 

src/main/scala/vexriscv/plugin/ShiftPlugins.scala

@@ -1,6 +1,6 @@
-package VexRiscv.Plugin
+package vexriscv.plugin
 
-import VexRiscv._
+import vexriscv._
 import spinal.core._
 import spinal.lib.Reverse
 

src/main/scala/vexriscv/plugin/SingleInstructionLimiterPlugin.scala

@@ -1,6 +1,6 @@
-package VexRiscv.Plugin
+package vexriscv.plugin
 
-import VexRiscv._
+import vexriscv._
 import spinal.core._
 import spinal.lib._
 

src/main/scala/vexriscv/plugin/SrcPlugin.scala

@@ -1,6 +1,6 @@
-package VexRiscv.Plugin
+package vexriscv.plugin
 
-import VexRiscv.{Riscv, VexRiscv}
+import vexriscv.{Riscv, VexRiscv}
 import spinal.core._
 
 

src/main/scala/vexriscv/plugin/StaticMemoryTranslatorPlugin.scala

@@ -1,6 +1,6 @@
-package VexRiscv.Plugin
+package vexriscv.plugin
 
-import VexRiscv.{VexRiscv, _}
+import vexriscv.{VexRiscv, _}
 import spinal.core._
 import spinal.lib._
 

src/main/scala/vexriscv/plugin/YamlPlugin.scala

@@ -1,8 +1,8 @@
-package VexRiscv.Plugin
+package vexriscv.plugin
 
 import java.util
 
-import VexRiscv.{ReportService, VexRiscv}
+import vexriscv.{ReportService, VexRiscv}
 import org.yaml.snakeyaml.{DumperOptions, Yaml}