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workaround AMO LR/SC consistancy issue, but that need a proper fix

This commit is contained in:
Dolu1990 2020-04-19 19:48:57 +02:00
parent af128ec9eb
commit a1b6353d6b
2 changed files with 10 additions and 8 deletions
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9
src/main/scala/vexriscv/ip/DataCache.scala
View File

@ -514,6 +514,7 @@ class DataCache(val p : DataCacheConfig) extends Component{
val counter = Reg(UInt(log2Up(pendingMax) + 1 bits)) init(0) val counter = Reg(UInt(log2Up(pendingMax) + 1 bits)) init(0)
counter := counter + U(io.mem.cmd.fire && io.mem.cmd.last) - U(io.mem.rsp.valid && io.mem.rsp.last) counter := counter + U(io.mem.cmd.fire && io.mem.cmd.last) - U(io.mem.rsp.valid && io.mem.rsp.last)
val consistent = counter === 0
val full = RegNext(counter.msb) val full = RegNext(counter.msb)
val last = counter === 1 val last = counter === 1
@ -533,6 +534,8 @@ class DataCache(val p : DataCacheConfig) extends Component{
val full = RegNext(counter.msb) val full = RegNext(counter.msb)
io.cpu.execute.haltIt setWhen(full) io.cpu.execute.haltIt setWhen(full)
val consistent = counter === 0
} }
@ -546,9 +549,9 @@ class DataCache(val p : DataCacheConfig) extends Component{
val wayInvalidate = B(0, wayCount bits) //Used if invalidate enabled val wayInvalidate = B(0, wayCount bits) //Used if invalidate enabled
when(io.cpu.execute.fence){ when(io.cpu.execute.fence){
val counter = if(withInvalidate) sync.counter else if(withWriteResponse) pending.counter else null val consistent = if(withInvalidate) sync.consistent else if(withWriteResponse) pending.consistent else null
if(counter != null){ if(consistent != null){
when(counter =/= 0 || io.cpu.memory.isValid || io.cpu.writeBack.isValid){ when(!consistent || io.cpu.memory.isValid && io.cpu.memory.isWrite || io.cpu.writeBack.isValid && io.cpu.memory.isWrite){
io.cpu.execute.haltIt := True io.cpu.execute.haltIt := True
} }
} }

9
src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
View File

@ -229,11 +229,10 @@ class DBusCachedPlugin(val config : DataCacheConfig,
val ff = input(INSTRUCTION)(31 downto 20).as(FenceFlags()) val ff = input(INSTRUCTION)(31 downto 20).as(FenceFlags())
if(withWriteResponse){ if(withWriteResponse){
hazard setWhen(input(MEMORY_FENCE) && (ff.PS && ff.SL)) //Manage write to read hit ordering (ensure invalidation timings) hazard setWhen(input(MEMORY_FENCE) && (ff.PS && ff.SL)) //Manage write to read hit ordering (ensure invalidation timings)
// Not required as LR SC AMO emited on the memory bus enforce the ordering, + it bypass the cache when(input(INSTRUCTION)(26 downto 25) =/= 0){
// when(input(INSTRUCTION)(26 downto 25) =/= 0){ if(withLrSc) hazard setWhen(input(MEMORY_LRSC))
// if(withLrSc) hazard setWhen(input(MEMORY_LRSC)) if(withAmo) hazard setWhen(input(MEMORY_AMO))
// if(withAmo) hazard setWhen(input(MEMORY_AMO)) }
// }
} }
insert(MEMORY_FENCE_DECODED) := hazard insert(MEMORY_FENCE_DECODED) := hazard
} }