comment debug code
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@ -1632,14 +1632,14 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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}
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}
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val csrs = (0x7A0 to 0x7A5)
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val miaouRead = csrs.map(v => isReading(v)).orR
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val miaouWrite = csrs.map(v => isWriting(v)).orR
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Component.toplevel.rework{
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out(CombInit(miaouRead.pull())).setName("debug0")
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out(CombInit(miaouWrite.pull())).setName("debug1")
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}
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// val csrs = (0x7A0 to 0x7A5)
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// val miaouRead = csrs.map(v => isReading(v)).orR
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// val miaouWrite = csrs.map(v => isWriting(v)).orR
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//
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// Component.toplevel.rework{
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// out(CombInit(miaouRead.pull())).setName("debug0")
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// out(CombInit(miaouWrite.pull())).setName("debug1")
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// }
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}
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}
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}
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