Move things into SpinalHDL lib

src/main/scala/vexriscv/VexRiscv.scala

@@ -22,6 +22,8 @@ case class VexRiscvConfig(){
   var withWriteBackStage = true
   val plugins = ArrayBuffer[Plugin[VexRiscv]]()
 
+  def add(that : Plugin[VexRiscv]) : this.type = {plugins += that;this}
+
   //Default Stageables
   object IS_RVC extends Stageable(Bool)
   object BYPASSABLE_EXECUTE_STAGE   extends Stageable(Bool)

src/main/scala/vexriscv/demo/Murax.scala

@@ -262,7 +262,7 @@ case class Murax(config : MuraxConfig) extends Component{
     )
     mainBusMapping += ram.io.bus -> (0x80000000l, onChipRamSize)
 
-    val apbBridge = new MuraxPipelinedMemoryBusToApbBridge(
+    val apbBridge = new PipelinedMemoryBusToApbBridge(
       apb3Config = Apb3Config(
         addressWidth = 20,
         dataWidth = 32

src/main/scala/vexriscv/demo/MuraxUtiles.scala

@@ -96,39 +96,7 @@ case class Apb3Rom(onChipRamBinFile : String) extends Component{
   io.apb.PREADY := True
 }
 
-class MuraxPipelinedMemoryBusToApbBridge(apb3Config: Apb3Config, pipelineBridge : Boolean, pipelinedMemoryBusConfig : PipelinedMemoryBusConfig) extends Component{
-  assert(apb3Config.dataWidth == pipelinedMemoryBusConfig.dataWidth)
 
-  val io = new Bundle {
-    val pipelinedMemoryBus = slave(PipelinedMemoryBus(pipelinedMemoryBusConfig))
-    val apb = master(Apb3(apb3Config))
-  }
-
-  val pipelinedMemoryBusStage = PipelinedMemoryBus(pipelinedMemoryBusConfig)
-  pipelinedMemoryBusStage.cmd << (if(pipelineBridge) io.pipelinedMemoryBus.cmd.halfPipe() else io.pipelinedMemoryBus.cmd)
-  pipelinedMemoryBusStage.rsp >-> io.pipelinedMemoryBus.rsp
-
-  val state = RegInit(False)
-  pipelinedMemoryBusStage.cmd.ready := False
-
-  io.apb.PSEL(0) := pipelinedMemoryBusStage.cmd.valid
-  io.apb.PENABLE := state
-  io.apb.PWRITE  := pipelinedMemoryBusStage.cmd.write
-  io.apb.PADDR   := pipelinedMemoryBusStage.cmd.address.resized
-  io.apb.PWDATA  := pipelinedMemoryBusStage.cmd.data
-
-  pipelinedMemoryBusStage.rsp.valid := False
-  pipelinedMemoryBusStage.rsp.data  := io.apb.PRDATA
-  when(!state) {
-    state := pipelinedMemoryBusStage.cmd.valid
-  } otherwise {
-    when(io.apb.PREADY){
-      state := False
-      pipelinedMemoryBusStage.rsp.valid := !pipelinedMemoryBusStage.cmd.write
-      pipelinedMemoryBusStage.cmd.ready := True
-    }
-  }
-}
 
 class MuraxPipelinedMemoryBusDecoder(master : PipelinedMemoryBus, val specification : Seq[(PipelinedMemoryBus,SizeMapping)], pipelineMaster : Boolean) extends Area{
   val masterPipelined = PipelinedMemoryBus(master.config)

src/test/scala/vexriscv/MuraxSim.scala

@@ -20,9 +20,9 @@ import scala.collection.mutable
 object MuraxSim {
   def main(args: Array[String]): Unit = {
 //    def config = MuraxConfig.default.copy(onChipRamSize = 256 kB)
-    def config = MuraxConfig.default(withXip = true).copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex")
+    def config = MuraxConfig.default(withXip = false).copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex")
-    val simSlowDown = true
+    val simSlowDown = false
-    SimConfig.allOptimisation.withWave.compile(new Murax(config)).doSimUntilVoid{dut =>
+    SimConfig.allOptimisation.compile(new Murax(config)).doSimUntilVoid{dut =>
       val mainClkPeriod = (1e12/dut.config.coreFrequency.toDouble).toLong
       val jtagClkPeriod = mainClkPeriod*4
       val uartBaudRate = 115200