Add Murax configuration which integrate a boot programme :
Will blink led and echo UART RX to UART TX (in the verilator sim, type some text and press enter to send UART frame to the Murax RX pin)
This commit is contained in:
Charles Papon
parent
58981c0e8e
commit
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@ -35,61 +35,61 @@ object TestsWorkspace {
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resetVector = 0x00000000l,
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relaxedPcCalculation = false
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),
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// new IBusSimplePlugin(
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// interfaceKeepData = false,
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// catchAccessFault = true
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// ),
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new IBusCachedPlugin(
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config = InstructionCacheConfig(
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cacheSize = 4096,
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bytePerLine =32,
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wayCount = 1,
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wrappedMemAccess = true,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchIllegalAccess = true,
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catchAccessFault = true,
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catchMemoryTranslationMiss = true,
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asyncTagMemory = false,
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twoStageLogic = true
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new IBusSimplePlugin(
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interfaceKeepData = false,
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catchAccessFault = true
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),
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askMemoryTranslation = true,
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memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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portTlbSize = 4
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)
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),
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// new DBusSimplePlugin(
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// catchAddressMisaligned = true,
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// new IBusCachedPlugin(
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// config = InstructionCacheConfig(
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// cacheSize = 4096,
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// bytePerLine =32,
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// wayCount = 1,
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// wrappedMemAccess = true,
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// addressWidth = 32,
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// cpuDataWidth = 32,
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// memDataWidth = 32,
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// catchIllegalAccess = true,
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// catchAccessFault = true,
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// earlyInjection = false
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// catchMemoryTranslationMiss = true,
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// asyncTagMemory = false,
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// twoStageLogic = true
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// ),
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new DBusCachedPlugin(
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config = new DataCacheConfig(
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cacheSize = 4096,
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bytePerLine = 32,
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wayCount = 1,
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addressWidth = 32,
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cpuDataWidth = 32,
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memDataWidth = 32,
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catchAccessError = true,
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catchIllegal = true,
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catchUnaligned = true,
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catchMemoryTranslationMiss = true
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),
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// memoryTranslatorPortConfig = null
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memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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portTlbSize = 6
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)
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// askMemoryTranslation = true,
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// memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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// portTlbSize = 4
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// )
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// ),
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new DBusSimplePlugin(
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catchAddressMisaligned = true,
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catchAccessFault = true,
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earlyInjection = false
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),
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// new DBusCachedPlugin(
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// config = new DataCacheConfig(
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// cacheSize = 4096,
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// bytePerLine = 32,
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// wayCount = 1,
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// addressWidth = 32,
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// cpuDataWidth = 32,
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// memDataWidth = 32,
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// catchAccessError = true,
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// catchIllegal = true,
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// catchUnaligned = true,
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// catchMemoryTranslationMiss = true
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// ),
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//// memoryTranslatorPortConfig = null
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// memoryTranslatorPortConfig = MemoryTranslatorPortConfig(
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// portTlbSize = 6
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// )
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// ),
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// new StaticMemoryTranslatorPlugin(
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// ioRange = _(31 downto 28) === 0xF
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// ),
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new MemoryTranslatorPlugin(
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tlbSize = 32,
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virtualRange = _(31 downto 28) === 0xC,
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ioRange = _(31 downto 28) === 0xF
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),
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// new MemoryTranslatorPlugin(
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// tlbSize = 32,
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// virtualRange = _(31 downto 28) === 0xC,
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// ioRange = _(31 downto 28) === 0xF
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// ),
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new DecoderSimplePlugin(
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catchIllegalInstruction = true
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),
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@ -30,6 +30,7 @@ import vexriscv.{plugin, VexRiscvConfig, VexRiscv}
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case class MuraxConfig(coreFrequency : HertzNumber,
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onChipRamSize : BigInt,
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onChipRamHexFile : String,
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bypassExecute : Boolean,
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bypassMemory: Boolean,
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bypassWriteBack: Boolean,
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@ -44,6 +45,7 @@ object MuraxConfig{
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def default = MuraxConfig(
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coreFrequency = 12 MHz,
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onChipRamSize = 8 kB,
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onChipRamHexFile = null,
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bypassExecute = false,
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bypassMemory = false,
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bypassWriteBack = false,
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@ -267,6 +269,40 @@ case class Murax(config : MuraxConfig) extends Component{
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mask = bus.cmd.mask
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)
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bus.cmd.ready := True
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if(onChipRamHexFile != null){
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def readHexFile(path : String, callback : (Int, Int) => Unit): Unit ={
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import scala.io.Source
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def hToI(that : String, start : Int, size : Int) = Integer.parseInt(that.substring(start,start + size), 16)
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var offset = 0
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for (line <- Source.fromFile(path).getLines) {
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if (line.charAt(0) == ':'){
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val byteCount = hToI(line, 1, 2)
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val nextAddr = hToI(line, 3, 4) + offset
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val key = hToI(line, 7, 2)
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key match {
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case 0 =>
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for(i <- 0 until byteCount){
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callback(nextAddr + i, hToI(line, 9 + i * 2, 2))
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}
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case 2 =>
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offset = hToI(line, 9, 4) << 4
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case 4 =>
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offset = hToI(line, 9, 4) << 16
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case 3 =>
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case 1 =>
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}
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}
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}
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}
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val initContent = Array.fill[BigInt](ram.wordCount)(0)
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readHexFile(onChipRamHexFile,(address,data) => {
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initContent(address >> 2) |= BigInt(data) << ((address & 3)*8)
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})
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ram.initBigInt(initContent)
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}
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}
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@ -420,3 +456,11 @@ object Murax{
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SpinalVerilog(Murax(MuraxConfig.default))
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}
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}
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//Will blink led and echo UART RX to UART TX (in the verilator sim, type some text and press enter to send UART frame to the Murax RX pin)
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object MuraxWithRamInit{
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def main(args: Array[String]) {
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SpinalVerilog(Murax(MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex")))
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}
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}
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