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VexRiscv
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Hazard on memory stage do not need to know if that's bypassable if the memory stage is the last one

This commit is contained in:
Charles Papon 2019-09-21 14:13:28 +02:00
parent e1795e59d5
commit ace963b542
1 changed files with 1 additions and 1 deletions
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2
src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala
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@ -95,7 +95,7 @@ class HazardSimplePlugin(bypassExecute : Boolean = false,
}
if(withWriteBackStage) trackHazardWithStage(writeBack,bypassWriteBack,null)
if(withMemoryStage) trackHazardWithStage(memory ,bypassMemory ,BYPASSABLE_MEMORY_STAGE)
if(withMemoryStage) trackHazardWithStage(memory ,bypassMemory, if(stages.last == memory) null else BYPASSABLE_MEMORY_STAGE)
if(readStage != execute) trackHazardWithStage(execute ,bypassExecute , if(stages.last == execute) null else BYPASSABLE_EXECUTE_STAGE)