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Enable RF bypass on MUL DIV with pipeline wihout writeback/memory stages

This commit is contained in:
Charles Papon 2019-09-21 13:00:54 +02:00
parent e8236dfebe
commit e1795e59d5
2 changed files with 3 additions and 3 deletions
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2
src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala
View File

@ -31,7 +31,7 @@ class MulDivIterativePlugin(genMul : Boolean = true,
SRC1_CTRL -> Src1CtrlEnum.RS,
SRC2_CTRL -> Src2CtrlEnum.RS,
REGFILE_WRITE_VALID -> True,
BYPASSABLE_EXECUTE_STAGE -> False,
BYPASSABLE_EXECUTE_STAGE -> Bool(pipeline.stages.last == pipeline.execute),
BYPASSABLE_MEMORY_STAGE -> True,
RS1_USE -> True,
RS2_USE -> True

4
src/main/scala/vexriscv/plugin/MulSimplePlugin.scala
View File

@ -19,8 +19,8 @@ class MulSimplePlugin extends Plugin[VexRiscv]{
SRC1_CTRL -> Src1CtrlEnum.RS,
SRC2_CTRL -> Src2CtrlEnum.RS,
REGFILE_WRITE_VALID -> True,
BYPASSABLE_EXECUTE_STAGE -> False,
BYPASSABLE_MEMORY_STAGE -> False,
BYPASSABLE_EXECUTE_STAGE -> Bool(pipeline.stages.last == pipeline.execute),
BYPASSABLE_MEMORY_STAGE -> Bool(pipeline.stages.last == pipeline.memory),
RS1_USE -> True,
RS2_USE -> True,
IS_MUL -> True