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FpuPlugin.pending is now 6 bits

This commit is contained in:
Charles Papon 2021-03-11 13:06:50 +01:00
parent 845cfcb966
commit adc37b269c
1 changed files with 1 additions and 1 deletions
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src/main/scala/vexriscv/plugin/FpuPlugin.scala
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@ -241,7 +241,7 @@ class FpuPlugin(externalFpu : Boolean = false,
val csr = pipeline plug new Area{ val csr = pipeline plug new Area{
val pendings = Reg(UInt(5 bits)) init(0) val pendings = Reg(UInt(6 bits)) init(0)
pendings := pendings + U(port.cmd.fire) - U(port.completion.fire) - U(port.rsp.fire) pendings := pendings + U(port.cmd.fire) - U(port.completion.fire) - U(port.rsp.fire)
val hasPending = pendings =/= 0 val hasPending = pendings =/= 0