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Add mmu test into the dhrystone regression command
This commit is contained in:
Dolu1990 2018-09-24 18:31:33 +02:00
parent 1e3b75ef1d
commit aff436ddcf
12 changed files with 34 additions and 33 deletions
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10
src/main/scala/vexriscv/TestsWorkspace.scala
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@ -28,7 +28,7 @@ import spinal.lib.eda.altera.{InterruptReceiverTag, ResetEmitterTag}
object TestsWorkspace { object TestsWorkspace {
def main(args: Array[String]) { def main(args: Array[String]) {
SpinalConfig(mergeAsyncProcess = false).generateVerilog { SpinalConfig(mergeAsyncProcess = false, anonymSignalPrefix = "zz_").generateVerilog {
val configFull = VexRiscvConfig( val configFull = VexRiscvConfig(
plugins = List( plugins = List(
// new IBusSimplePlugin( // new IBusSimplePlugin(
@ -44,11 +44,11 @@ object TestsWorkspace {
// ), // ),
new IBusCachedPlugin( new IBusCachedPlugin(
resetVector = 0x80000000l, resetVector = 0x80000000l,
compressedGen = true, compressedGen = false,
prediction = DYNAMIC_TARGET, prediction = NONE,
injectorStage = true, injectorStage = true,
config = InstructionCacheConfig( config = InstructionCacheConfig(
cacheSize = 1024*16, cacheSize = 4096,
bytePerLine = 32, bytePerLine = 32,
wayCount = 1, wayCount = 1,
addressWidth = 32, addressWidth = 32,
@ -72,7 +72,7 @@ object TestsWorkspace {
// ), // ),
new DBusCachedPlugin( new DBusCachedPlugin(
config = new DataCacheConfig( config = new DataCacheConfig(
cacheSize = 4096*4, cacheSize = 4096,
bytePerLine = 32, bytePerLine = 32,
wayCount = 1, wayCount = 1,
addressWidth = 32, addressWidth = 32,

4
src/main/scala/vexriscv/demo/GenFull.scala
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@ -54,7 +54,7 @@ object GenFull extends App{
) )
), ),
new MemoryTranslatorPlugin( new MemoryTranslatorPlugin(
tlbSize = 64, tlbSize = 32,
virtualRange = _(31 downto 28) === 0xC, virtualRange = _(31 downto 28) === 0xC,
ioRange = _(31 downto 28) === 0xF ioRange = _(31 downto 28) === 0xF
), ),
@ -82,7 +82,7 @@ object GenFull extends App{
), ),
new MulPlugin, new MulPlugin,
new DivPlugin, new DivPlugin,
new CsrPlugin(CsrPluginConfig.small), new CsrPlugin(CsrPluginConfig.small(0x80000020l)),
new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
new BranchPlugin( new BranchPlugin(
earlyBranch = false, earlyBranch = false,

6
src/main/scala/vexriscv/demo/Murax.scala
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@ -43,7 +43,7 @@ case class MuraxConfig(coreFrequency : HertzNumber,
hardwareBreakpointCount : Int, hardwareBreakpointCount : Int,
cpuPlugins : ArrayBuffer[Plugin[VexRiscv]]){ cpuPlugins : ArrayBuffer[Plugin[VexRiscv]]){
require(pipelineApbBridge || pipelineMainBus, "At least pipelineMainBus or pipelineApbBridge should be enable to avoid wipe transactions") require(pipelineApbBridge || pipelineMainBus, "At least pipelineMainBus or pipelineApbBridge should be enable to avoid wipe transactions")
val genXpi = xipConfig != null val genXip = xipConfig != null
} }
@ -162,7 +162,7 @@ case class Murax(config : MuraxConfig) extends Component{
val gpioA = master(TriStateArray(gpioWidth bits)) val gpioA = master(TriStateArray(gpioWidth bits))
val uart = master(Uart()) val uart = master(Uart())
val xip = ifGen(genXpi)(master(SpiDdrMaster(xipConfig.ctrl.spi))) val xip = ifGen(genXip)(master(SpiDdrMaster(xipConfig.ctrl.spi)))
} }
@ -286,7 +286,7 @@ case class Murax(config : MuraxConfig) extends Component{
timerInterrupt setWhen(timer.io.interrupt) timerInterrupt setWhen(timer.io.interrupt)
apbMapping += timer.io.apb -> (0x20000, 4 kB) apbMapping += timer.io.apb -> (0x20000, 4 kB)
val xip = ifGen(genXpi)(new Area{ val xip = ifGen(genXip)(new Area{
val ctrl = Apb3SpiDdrMasterCtrl(xipConfig) val ctrl = Apb3SpiDdrMasterCtrl(xipConfig)
ctrl.io.spi <> io.xip ctrl.io.spi <> io.xip
externalInterrupt setWhen(ctrl.io.interrupt) externalInterrupt setWhen(ctrl.io.interrupt)

10
src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala
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@ -141,31 +141,31 @@ object VexRiscvAvalonForSim{
var iBus : AvalonMM = null var iBus : AvalonMM = null
for (plugin <- cpuConfig.plugins) plugin match { for (plugin <- cpuConfig.plugins) plugin match {
case plugin: IBusSimplePlugin => { case plugin: IBusSimplePlugin => {
plugin.iBus.asDirectionLess() //Unset IO properties of iBus plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
iBus = master(plugin.iBus.toAvalon()) iBus = master(plugin.iBus.toAvalon())
.setName("iBusAvalon") .setName("iBusAvalon")
.addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify) .addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
} }
case plugin: IBusCachedPlugin => { case plugin: IBusCachedPlugin => {
plugin.iBus.asDirectionLess() //Unset IO properties of iBus plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
iBus = master(plugin.iBus.toAvalon()) iBus = master(plugin.iBus.toAvalon())
.setName("iBusAvalon") .setName("iBusAvalon")
.addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify) .addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
} }
case plugin: DBusSimplePlugin => { case plugin: DBusSimplePlugin => {
plugin.dBus.asDirectionLess() plugin.dBus.setAsDirectionLess()
master(plugin.dBus.toAvalon()) master(plugin.dBus.toAvalon())
.setName("dBusAvalon") .setName("dBusAvalon")
.addTag(ClockDomainTag(ClockDomain.current)) .addTag(ClockDomainTag(ClockDomain.current))
} }
case plugin: DBusCachedPlugin => { case plugin: DBusCachedPlugin => {
plugin.dBus.asDirectionLess() plugin.dBus.setAsDirectionLess()
master(plugin.dBus.toAvalon()) master(plugin.dBus.toAvalon())
.setName("dBusAvalon") .setName("dBusAvalon")
.addTag(ClockDomainTag(ClockDomain.current)) .addTag(ClockDomainTag(ClockDomain.current))
} }
case plugin: DebugPlugin => { case plugin: DebugPlugin => {
plugin.io.bus.asDirectionLess() plugin.io.bus.setAsDirectionLess()
slave(plugin.io.bus.fromAvalon()) slave(plugin.io.bus.fromAvalon())
.setName("debugBusAvalon") .setName("debugBusAvalon")
.addTag(ClockDomainTag(plugin.debugClockDomain)) .addTag(ClockDomainTag(plugin.debugClockDomain))

10
src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala
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@ -139,31 +139,31 @@ object VexRiscvAvalonWithIntegratedJtag{
var iBus : AvalonMM = null var iBus : AvalonMM = null
for (plugin <- cpuConfig.plugins) plugin match { for (plugin <- cpuConfig.plugins) plugin match {
case plugin: IBusSimplePlugin => { case plugin: IBusSimplePlugin => {
plugin.iBus.asDirectionLess() //Unset IO properties of iBus plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
iBus = master(plugin.iBus.toAvalon()) iBus = master(plugin.iBus.toAvalon())
.setName("iBusAvalon") .setName("iBusAvalon")
.addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify) .addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
} }
case plugin: IBusCachedPlugin => { case plugin: IBusCachedPlugin => {
plugin.iBus.asDirectionLess() //Unset IO properties of iBus plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
iBus = master(plugin.iBus.toAvalon()) iBus = master(plugin.iBus.toAvalon())
.setName("iBusAvalon") .setName("iBusAvalon")
.addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify) .addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
} }
case plugin: DBusSimplePlugin => { case plugin: DBusSimplePlugin => {
plugin.dBus.asDirectionLess() plugin.dBus.setAsDirectionLess()
master(plugin.dBus.toAvalon()) master(plugin.dBus.toAvalon())
.setName("dBusAvalon") .setName("dBusAvalon")
.addTag(ClockDomainTag(ClockDomain.current)) .addTag(ClockDomainTag(ClockDomain.current))
} }
case plugin: DBusCachedPlugin => { case plugin: DBusCachedPlugin => {
plugin.dBus.asDirectionLess() plugin.dBus.setAsDirectionLess()
master(plugin.dBus.toAvalon()) master(plugin.dBus.toAvalon())
.setName("dBusAvalon") .setName("dBusAvalon")
.addTag(ClockDomainTag(ClockDomain.current)) .addTag(ClockDomainTag(ClockDomain.current))
} }
case plugin: DebugPlugin => { case plugin: DebugPlugin => {
plugin.io.bus.asDirectionLess() plugin.io.bus.setAsDirectionLess()
val jtag = slave(new Jtag()) val jtag = slave(new Jtag())
.setName("jtag") .setName("jtag")
jtag <> plugin.io.bus.fromJtag() jtag <> plugin.io.bus.fromJtag()

10
src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala
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@ -140,31 +140,31 @@ object VexRiscvAxi4WithIntegratedJtag{
var iBus : Axi4ReadOnly = null var iBus : Axi4ReadOnly = null
for (plugin <- cpuConfig.plugins) plugin match { for (plugin <- cpuConfig.plugins) plugin match {
case plugin: IBusSimplePlugin => { case plugin: IBusSimplePlugin => {
plugin.iBus.asDirectionLess() //Unset IO properties of iBus plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
iBus = master(plugin.iBus.toAxi4ReadOnly().toFullConfig()) iBus = master(plugin.iBus.toAxi4ReadOnly().toFullConfig())
.setName("iBusAxi") .setName("iBusAxi")
.addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify) .addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
} }
case plugin: IBusCachedPlugin => { case plugin: IBusCachedPlugin => {
plugin.iBus.asDirectionLess() //Unset IO properties of iBus plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
iBus = master(plugin.iBus.toAxi4ReadOnly().toFullConfig()) iBus = master(plugin.iBus.toAxi4ReadOnly().toFullConfig())
.setName("iBusAxi") .setName("iBusAxi")
.addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify) .addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
} }
case plugin: DBusSimplePlugin => { case plugin: DBusSimplePlugin => {
plugin.dBus.asDirectionLess() plugin.dBus.setAsDirectionLess()
master(plugin.dBus.toAxi4Shared().toAxi4().toFullConfig()) master(plugin.dBus.toAxi4Shared().toAxi4().toFullConfig())
.setName("dBusAxi") .setName("dBusAxi")
.addTag(ClockDomainTag(ClockDomain.current)) .addTag(ClockDomainTag(ClockDomain.current))
} }
case plugin: DBusCachedPlugin => { case plugin: DBusCachedPlugin => {
plugin.dBus.asDirectionLess() plugin.dBus.setAsDirectionLess()
master(plugin.dBus.toAxi4Shared().toAxi4().toFullConfig()) master(plugin.dBus.toAxi4Shared().toAxi4().toFullConfig())
.setName("dBusAxi") .setName("dBusAxi")
.addTag(ClockDomainTag(ClockDomain.current)) .addTag(ClockDomainTag(ClockDomain.current))
} }
case plugin: DebugPlugin => { case plugin: DebugPlugin => {
plugin.io.bus.asDirectionLess() plugin.io.bus.setAsDirectionLess()
val jtag = slave(new Jtag()) val jtag = slave(new Jtag())
.setName("jtag") .setName("jtag")
jtag <> plugin.io.bus.fromJtag() jtag <> plugin.io.bus.fromJtag()

8
src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala
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@ -118,19 +118,19 @@ object VexRiscvCachedWishboneForSim{
cpu.rework { cpu.rework {
for (plugin <- cpuConfig.plugins) plugin match { for (plugin <- cpuConfig.plugins) plugin match {
case plugin: IBusSimplePlugin => { case plugin: IBusSimplePlugin => {
plugin.iBus.asDirectionLess() //Unset IO properties of iBus plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
master(plugin.iBus.toWishbone()).setName("iBusWishbone") master(plugin.iBus.toWishbone()).setName("iBusWishbone")
} }
case plugin: IBusCachedPlugin => { case plugin: IBusCachedPlugin => {
plugin.iBus.asDirectionLess() plugin.iBus.setAsDirectionLess()
master(plugin.iBus.toWishbone()).setName("iBusWishbone") master(plugin.iBus.toWishbone()).setName("iBusWishbone")
} }
case plugin: DBusSimplePlugin => { case plugin: DBusSimplePlugin => {
plugin.dBus.asDirectionLess() plugin.dBus.setAsDirectionLess()
master(plugin.dBus.toWishbone()).setName("dBusWishbone") master(plugin.dBus.toWishbone()).setName("dBusWishbone")
} }
case plugin: DBusCachedPlugin => { case plugin: DBusCachedPlugin => {
plugin.dBus.asDirectionLess() plugin.dBus.setAsDirectionLess()
master(plugin.dBus.toWishbone()).setName("dBusWishbone") master(plugin.dBus.toWishbone()).setName("dBusWishbone")
} }
case _ => case _ =>

2
src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
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@ -12,7 +12,7 @@ class DAxiCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An
override def build(pipeline: VexRiscv): Unit = { override def build(pipeline: VexRiscv): Unit = {
super.build(pipeline) super.build(pipeline)
dBus.asDirectionLess() dBus.setAsDirectionLess()
dAxi = master(dBus.toAxi4Shared().toAxi4()).setName("dAxi") dAxi = master(dBus.toAxi4Shared().toAxi4()).setName("dAxi")
dBus = null //For safety, as nobody should use it anymore :) dBus = null //For safety, as nobody should use it anymore :)
} }

2
src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala
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@ -151,7 +151,7 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean = false, forceLegalI
import toplevel.config._ import toplevel.config._
toplevel.getAllIo.foreach{io => toplevel.getAllIo.foreach{io =>
if(io.isInput) io.assignDontCare() if(io.isInput) io.assignDontCare()
io.asDirectionLess() io.setAsDirectionLess()
} }
toplevel.decode.input(INSTRUCTION).removeAssignments() toplevel.decode.input(INSTRUCTION).removeAssignments()
toplevel.decode.input(INSTRUCTION) := Delay((in Bits(32 bits)).setName("instruction"),2) toplevel.decode.input(INSTRUCTION) := Delay((in Bits(32 bits)).setName("instruction"),2)

2
src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala
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@ -14,7 +14,7 @@ class ExternalInterruptArrayPlugin(arrayWidth : Int = 32, maskCsrId : Int = 0xBC
val csr = pipeline.service(classOf[CsrPlugin]) val csr = pipeline.service(classOf[CsrPlugin])
val mask = Reg(Bits(arrayWidth bits)) init(0) val mask = Reg(Bits(arrayWidth bits)) init(0)
val pendings = mask & RegNext(externalInterruptArray) val pendings = mask & RegNext(externalInterruptArray)
csr.externalInterrupt.asDirectionLess() := pendings.orR csr.externalInterrupt.setAsDirectionLess() := pendings.orR
csr.rw(maskCsrId, mask) csr.rw(maskCsrId, mask)
csr.r(pendingsCsrId, pendings) csr.r(pendingsCsrId, pendings)
} }

1
src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala
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@ -129,6 +129,7 @@ class MemoryTranslatorPlugin(tlbSize : Int,
} }
//Manage TLBW0 and TLBW1 instructions //Manage TLBW0 and TLBW1 instructions
//TODO not exception safe (sideeffect)
execute plug new Area{ execute plug new Area{
import execute._ import execute._
val tlbWriteBuffer = Reg(UInt(20 bits)) val tlbWriteBuffer = Reg(UInt(20 bits))

2
src/test/scala/vexriscv/DhrystoneBench.scala
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@ -89,7 +89,7 @@ class DhrystoneBench extends FunSuite{
getDmips( getDmips(
name = "GenFull", name = "GenFull",
gen = GenFull.main(null), gen = GenFull.main(null),
testCmd = "make clean run REDO=10 CSR=no MMU=no" testCmd = "make clean run REDO=10 CSR=no"
) )
test("final_report") { test("final_report") {