Hardware
/
VexRiscv
mirror of https://github.com/SpinalHDL/VexRiscv.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Sync with SpinalHDL head 

Add mmu test into the dhrystone regression command
This commit is contained in:
Dolu1990 2018-09-24 18:31:33 +02:00
parent 1e3b75ef1d
commit aff436ddcf
12 changed files with 34 additions and 33 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/main/scala/vexriscv/TestsWorkspace.scala
View File

@ -28,7 +28,7 @@ import spinal.lib.eda.altera.{InterruptReceiverTag, ResetEmitterTag}
object TestsWorkspace {
def main(args: Array[String]) {
SpinalConfig(mergeAsyncProcess = false).generateVerilog {
SpinalConfig(mergeAsyncProcess = false, anonymSignalPrefix = "zz_").generateVerilog {
val configFull = VexRiscvConfig(
plugins = List(
// new IBusSimplePlugin(
@ -44,11 +44,11 @@ object TestsWorkspace {
// ),
new IBusCachedPlugin(
resetVector = 0x80000000l,
compressedGen = true,
prediction = DYNAMIC_TARGET,
compressedGen = false,
prediction = NONE,
injectorStage = true,
config = InstructionCacheConfig(
cacheSize = 1024*16,
cacheSize = 4096,
bytePerLine = 32,
wayCount = 1,
addressWidth = 32,
@ -72,7 +72,7 @@ object TestsWorkspace {
// ),
new DBusCachedPlugin(
config = new DataCacheConfig(
cacheSize = 4096*4,
cacheSize = 4096,
bytePerLine = 32,
wayCount = 1,
addressWidth = 32,

4
src/main/scala/vexriscv/demo/GenFull.scala
View File

@ -54,7 +54,7 @@ object GenFull extends App{
)
),
new MemoryTranslatorPlugin(
tlbSize = 64,
tlbSize = 32,
virtualRange = _(31 downto 28) === 0xC,
ioRange = _(31 downto 28) === 0xF
),
@ -82,7 +82,7 @@ object GenFull extends App{
),
new MulPlugin,
new DivPlugin,
new CsrPlugin(CsrPluginConfig.small),
new CsrPlugin(CsrPluginConfig.small(0x80000020l)),
new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))),
new BranchPlugin(
earlyBranch = false,

6
src/main/scala/vexriscv/demo/Murax.scala
View File

@ -43,7 +43,7 @@ case class MuraxConfig(coreFrequency : HertzNumber,
hardwareBreakpointCount : Int,
cpuPlugins : ArrayBuffer[Plugin[VexRiscv]]){
require(pipelineApbBridge || pipelineMainBus, "At least pipelineMainBus or pipelineApbBridge should be enable to avoid wipe transactions")
val genXpi = xipConfig != null
val genXip = xipConfig != null
}
@ -162,7 +162,7 @@ case class Murax(config : MuraxConfig) extends Component{
val gpioA = master(TriStateArray(gpioWidth bits))
val uart = master(Uart())
val xip = ifGen(genXpi)(master(SpiDdrMaster(xipConfig.ctrl.spi)))
val xip = ifGen(genXip)(master(SpiDdrMaster(xipConfig.ctrl.spi)))
}
@ -286,7 +286,7 @@ case class Murax(config : MuraxConfig) extends Component{
timerInterrupt setWhen(timer.io.interrupt)
apbMapping += timer.io.apb -> (0x20000, 4 kB)
val xip = ifGen(genXpi)(new Area{
val xip = ifGen(genXip)(new Area{
val ctrl = Apb3SpiDdrMasterCtrl(xipConfig)
ctrl.io.spi <> io.xip
externalInterrupt setWhen(ctrl.io.interrupt)

10
src/main/scala/vexriscv/demo/VexRiscvAvalonForSim.scala
View File

@ -141,31 +141,31 @@ object VexRiscvAvalonForSim{
var iBus : AvalonMM = null
for (plugin <- cpuConfig.plugins) plugin match {
case plugin: IBusSimplePlugin => {
plugin.iBus.asDirectionLess() //Unset IO properties of iBus
plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
iBus = master(plugin.iBus.toAvalon())
.setName("iBusAvalon")
.addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
}
case plugin: IBusCachedPlugin => {
plugin.iBus.asDirectionLess() //Unset IO properties of iBus
plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
iBus = master(plugin.iBus.toAvalon())
.setName("iBusAvalon")
.addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
}
case plugin: DBusSimplePlugin => {
plugin.dBus.asDirectionLess()
plugin.dBus.setAsDirectionLess()
master(plugin.dBus.toAvalon())
.setName("dBusAvalon")
.addTag(ClockDomainTag(ClockDomain.current))
}
case plugin: DBusCachedPlugin => {
plugin.dBus.asDirectionLess()
plugin.dBus.setAsDirectionLess()
master(plugin.dBus.toAvalon())
.setName("dBusAvalon")
.addTag(ClockDomainTag(ClockDomain.current))
}
case plugin: DebugPlugin => {
plugin.io.bus.asDirectionLess()
plugin.io.bus.setAsDirectionLess()
slave(plugin.io.bus.fromAvalon())
.setName("debugBusAvalon")
.addTag(ClockDomainTag(plugin.debugClockDomain))

10
src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala
View File

@ -139,31 +139,31 @@ object VexRiscvAvalonWithIntegratedJtag{
var iBus : AvalonMM = null
for (plugin <- cpuConfig.plugins) plugin match {
case plugin: IBusSimplePlugin => {
plugin.iBus.asDirectionLess() //Unset IO properties of iBus
plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
iBus = master(plugin.iBus.toAvalon())
.setName("iBusAvalon")
.addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
}
case plugin: IBusCachedPlugin => {
plugin.iBus.asDirectionLess() //Unset IO properties of iBus
plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
iBus = master(plugin.iBus.toAvalon())
.setName("iBusAvalon")
.addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
}
case plugin: DBusSimplePlugin => {
plugin.dBus.asDirectionLess()
plugin.dBus.setAsDirectionLess()
master(plugin.dBus.toAvalon())
.setName("dBusAvalon")
.addTag(ClockDomainTag(ClockDomain.current))
}
case plugin: DBusCachedPlugin => {
plugin.dBus.asDirectionLess()
plugin.dBus.setAsDirectionLess()
master(plugin.dBus.toAvalon())
.setName("dBusAvalon")
.addTag(ClockDomainTag(ClockDomain.current))
}
case plugin: DebugPlugin => {
plugin.io.bus.asDirectionLess()
plugin.io.bus.setAsDirectionLess()
val jtag = slave(new Jtag())
.setName("jtag")
jtag <> plugin.io.bus.fromJtag()

10
src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala
View File

@ -140,31 +140,31 @@ object VexRiscvAxi4WithIntegratedJtag{
var iBus : Axi4ReadOnly = null
for (plugin <- cpuConfig.plugins) plugin match {
case plugin: IBusSimplePlugin => {
plugin.iBus.asDirectionLess() //Unset IO properties of iBus
plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
iBus = master(plugin.iBus.toAxi4ReadOnly().toFullConfig())
.setName("iBusAxi")
.addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
}
case plugin: IBusCachedPlugin => {
plugin.iBus.asDirectionLess() //Unset IO properties of iBus
plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
iBus = master(plugin.iBus.toAxi4ReadOnly().toFullConfig())
.setName("iBusAxi")
.addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify)
}
case plugin: DBusSimplePlugin => {
plugin.dBus.asDirectionLess()
plugin.dBus.setAsDirectionLess()
master(plugin.dBus.toAxi4Shared().toAxi4().toFullConfig())
.setName("dBusAxi")
.addTag(ClockDomainTag(ClockDomain.current))
}
case plugin: DBusCachedPlugin => {
plugin.dBus.asDirectionLess()
plugin.dBus.setAsDirectionLess()
master(plugin.dBus.toAxi4Shared().toAxi4().toFullConfig())
.setName("dBusAxi")
.addTag(ClockDomainTag(ClockDomain.current))
}
case plugin: DebugPlugin => {
plugin.io.bus.asDirectionLess()
plugin.io.bus.setAsDirectionLess()
val jtag = slave(new Jtag())
.setName("jtag")
jtag <> plugin.io.bus.fromJtag()

8
src/main/scala/vexriscv/demo/VexRiscvCachedWishboneForSim.scala
View File

@ -118,19 +118,19 @@ object VexRiscvCachedWishboneForSim{
cpu.rework {
for (plugin <- cpuConfig.plugins) plugin match {
case plugin: IBusSimplePlugin => {
plugin.iBus.asDirectionLess() //Unset IO properties of iBus
plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus
master(plugin.iBus.toWishbone()).setName("iBusWishbone")
}
case plugin: IBusCachedPlugin => {
plugin.iBus.asDirectionLess()
plugin.iBus.setAsDirectionLess()
master(plugin.iBus.toWishbone()).setName("iBusWishbone")
}
case plugin: DBusSimplePlugin => {
plugin.dBus.asDirectionLess()
plugin.dBus.setAsDirectionLess()
master(plugin.dBus.toWishbone()).setName("dBusWishbone")
}
case plugin: DBusCachedPlugin => {
plugin.dBus.asDirectionLess()
plugin.dBus.setAsDirectionLess()
master(plugin.dBus.toWishbone()).setName("dBusWishbone")
}
case _ =>

2
src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
View File

@ -12,7 +12,7 @@ class DAxiCachedPlugin(config : DataCacheConfig, memoryTranslatorPortConfig : An
override def build(pipeline: VexRiscv): Unit = {
super.build(pipeline)
dBus.asDirectionLess()
dBus.setAsDirectionLess()
dAxi = master(dBus.toAxi4Shared().toAxi4()).setName("dAxi")
dBus = null //For safety, as nobody should use it anymore :)
}

2
src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala
View File

@ -151,7 +151,7 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean = false, forceLegalI
import toplevel.config._
toplevel.getAllIo.foreach{io =>
if(io.isInput) io.assignDontCare()
io.asDirectionLess()
io.setAsDirectionLess()
}
toplevel.decode.input(INSTRUCTION).removeAssignments()
toplevel.decode.input(INSTRUCTION) := Delay((in Bits(32 bits)).setName("instruction"),2)

2
src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala
View File

@ -14,7 +14,7 @@ class ExternalInterruptArrayPlugin(arrayWidth : Int = 32, maskCsrId : Int = 0xBC
val csr = pipeline.service(classOf[CsrPlugin])
val mask = Reg(Bits(arrayWidth bits)) init(0)
val pendings = mask & RegNext(externalInterruptArray)
csr.externalInterrupt.asDirectionLess() := pendings.orR
csr.externalInterrupt.setAsDirectionLess() := pendings.orR
csr.rw(maskCsrId, mask)
csr.r(pendingsCsrId, pendings)
}

1
src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala
View File

@ -129,6 +129,7 @@ class MemoryTranslatorPlugin(tlbSize : Int,
}
//Manage TLBW0 and TLBW1 instructions
//TODO not exception safe (sideeffect)
execute plug new Area{
import execute._
val tlbWriteBuffer = Reg(UInt(20 bits))

2
src/test/scala/vexriscv/DhrystoneBench.scala
View File

@ -89,7 +89,7 @@ class DhrystoneBench extends FunSuite{
getDmips(
name = "GenFull",
gen = GenFull.main(null),
testCmd = "make clean run REDO=10 CSR=no MMU=no"
testCmd = "make clean run REDO=10 CSR=no"
)
test("final_report") {