#60 Fix missing ecallGen flag
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@ -58,13 +58,13 @@ git clone https://github.com/SpinalHDL/buildroot.git -b vexriscv
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cd buildroot
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make spinal_vexriscv_sim_defconfig
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make -j$(nproc)
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output/host/bin/riscv32-linux-objcopy -O binary output/images/vmlinux output/images/vmlinux.bin
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output/host/bin/riscv32-linux-objcopy -O binary output/images/vmlinux output/images/Image
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After changing a kernel config into buildroot =>
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cd buildroot
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make spinal_vexriscv_sim_defconfig
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make linux-dirclean linux-rebuild -j8
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output/host/bin/riscv32-linux-objcopy -O binary output/images/vmlinux output/images/vmlinux.bin
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output/host/bin/riscv32-linux-objcopy -O binary output/images/vmlinux output/images/Image
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Compiling the machine mode emulator (check the config.h file to know the mode) =>
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cd src/main/c/emulator
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@ -92,7 +92,7 @@ export DATA=/home/miaou/Downloads/Binaries-master
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cd src/test/cpp/regression
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rm VexRiscv.v
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cp $DATA/VexRiscv.v ../../../..
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make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes COMPRESSED=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes EMULATOR=$DATA/emulator.bin VMLINUX=$DATA/vmlinux.bin DTB=$DATA/rv32.dtb RAMDISK=$DATA/rootfs.cpio TRACE=no FLOW_INFO=no
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make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD SUPERVISOR=yes CSR=yes COMPRESSED=yess LRSC=yes AMO=yes REDO=0 DHRYSTONE=no LINUX_SOC=yes EMULATOR=$DATA/emulator.bin VMLINUX=$DATA/vmlinux.bin DTB=$DATA/rv32.dtb RAMDISK=$DATA/rootfs.cpio TRACE=no FLOW_INFO=no
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qemu-system-riscv32 -nographic -machine virt -m 1536M -device loader,file=$DATA/emulator.bin,addr=0x80000000,cpu-num=0 -device loader,file=$DATA/rv32.dtb,addr=0xC3000000 -device loader,file=$DATA/vmlinux.bin,addr=0xC0000000 -device loader,file=$DATA/rootfs.cpio,addr=0xc2000000
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@ -96,7 +96,7 @@ object CsrPluginConfig{
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minstretAccess = CsrAccess.NONE,
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ucycleAccess = CsrAccess.NONE,
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wfiGenAsWait = true,
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ecallGen = false,
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ecallGen = true,
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xtvecModeGen = false,
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noCsrAlu = false,
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wfiGenAsNop = false,
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