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#60 Fix SFENCE_VMA deadlock

This commit is contained in:
Charles Papon 2019-04-18 18:33:06 +02:00
parent 6f04c02cd2
commit b79b02152b
1 changed files with 3 additions and 4 deletions
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7
src/main/scala/vexriscv/plugin/MmuPlugin.scala
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@ -253,10 +253,9 @@ class MmuPlugin(ioRange : UInt => Bool,
} }
} }
execute plug new Area{ writeBack plug new Area{
import execute._ import writeBack._
val tlbWriteBuffer = Reg(UInt(20 bits)) when(arbitration.isValid && input(IS_SFENCE_VMA)){ // || csrService.isWriting(CSR.SATP)
when(arbitration.isFiring && input(IS_SFENCE_VMA)){ // || csrService.isWriting(CSR.SATP)
for(port <- core.ports; line <- port.cache) line.valid := False //Assume that the instruction already fetched into the pipeline are ok for(port <- core.ports; line <- port.cache) line.valid := False //Assume that the instruction already fetched into the pipeline are ok
} }
} }