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VexRiscv
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few fixes

This commit is contained in:
Dolu1990 2020-04-16 01:29:13 +02:00
parent 46207abbc4
commit b9ceabf128
4 changed files with 19 additions and 3 deletions
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2
src/main/scala/vexriscv/ip/InstructionCache.scala
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@ -251,7 +251,7 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
def toBmb() : Bmb = { def toBmb() : Bmb = {
val busParameter = p.getBmbParameter val busParameter = p.getBmbParameter
val bus = Bmb(busParameter) val bus = Bmb(busParameter).setCompositeName(this,"toBmb", true)
bus.cmd.arbitrationFrom(cmd) bus.cmd.arbitrationFrom(cmd)
bus.cmd.opcode := Bmb.Cmd.Opcode.READ bus.cmd.opcode := Bmb.Cmd.Opcode.READ
bus.cmd.address := cmd.address.resized bus.cmd.address := cmd.address.resized

2
src/main/scala/vexriscv/plugin/DebugPlugin.scala
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@ -96,7 +96,7 @@ case class DebugExtensionIo() extends Bundle with IMasterSlave{
class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount : Int = 0) extends Plugin[VexRiscv] { class DebugPlugin(var debugClockDomain : ClockDomain, hardwareBreakpointCount : Int = 0) extends Plugin[VexRiscv] {
var io : DebugExtensionIo = null var io : DebugExtensionIo = null
val injectionAsks = ArrayBuffer[(Stage, Bool)]() val injectionAsks = ArrayBuffer[(Stage, Bool)]()

2
src/test/cpp/raw/common/asm.mk
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@ -40,7 +40,7 @@ OBJS := $(addprefix $(OBJDIR)/,$(OBJS))
all: $(OBJDIR)/$(PROJ_NAME).elf $(OBJDIR)/$(PROJ_NAME).hex $(OBJDIR)/$(PROJ_NAME).asm all: $(OBJDIR)/$(PROJ_NAME).elf $(OBJDIR)/$(PROJ_NAME).hex $(OBJDIR)/$(PROJ_NAME).asm $(OBJDIR)/$(PROJ_NAME).bin
@echo "done" @echo "done"
$(OBJDIR)/%.elf: $(OBJS) | $(OBJDIR) $(OBJDIR)/%.elf: $(OBJS) | $(OBJDIR)

16
src/test/cpp/regression/main.cpp
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@ -2350,6 +2350,7 @@ public:
bool reservationValid = false; bool reservationValid = false;
uint32_t reservationAddress; uint32_t reservationAddress;
uint32_t pendingSync = 0;
Workspace *ws; Workspace *ws;
VVexRiscv* top; VVexRiscv* top;
@ -2363,11 +2364,17 @@ public:
virtual void onReset(){ virtual void onReset(){
top->dBus_cmd_ready = 1; top->dBus_cmd_ready = 1;
top->dBus_rsp_valid = 0; top->dBus_rsp_valid = 0;
top->dBus_inv_valid = 0;
top->dBus_ack_ready = 0;
top->dBus_sync_valid = 0;
} }
virtual void preCycle(){ virtual void preCycle(){
if (top->dBus_cmd_valid && top->dBus_cmd_ready) { if (top->dBus_cmd_valid && top->dBus_cmd_ready) {
if(top->dBus_cmd_payload_wr){ if(top->dBus_cmd_payload_wr){
#ifdef DBUS_INVALIDATE
pendingSync += 1;
#endif
#ifndef DBUS_EXCLUSIVE #ifndef DBUS_EXCLUSIVE
bool error; bool error;
ws->dBusAccess(top->dBus_cmd_payload_address,1,2,top->dBus_cmd_payload_mask,&top->dBus_cmd_payload_data,&error); ws->dBusAccess(top->dBus_cmd_payload_address,1,2,top->dBus_cmd_payload_mask,&top->dBus_cmd_payload_data,&error);
@ -2406,6 +2413,11 @@ public:
#endif #endif
} }
} }
#ifdef DBUS_INVALIDATE
if(top->dBus_sync_valid && top->dBus_sync_ready){
pendingSync -= 1;
}
#endif
} }
virtual void postCycle(){ virtual void postCycle(){
@ -2446,6 +2458,10 @@ public:
} }
} }
top->dBus_ack_ready = (ws->dStall ? VL_RANDOM_I(7) < 100 : 1); top->dBus_ack_ready = (ws->dStall ? VL_RANDOM_I(7) < 100 : 1);
if(top->dBus_sync_ready) top->dBus_sync_valid = 0;
if(top->dBus_sync_valid == 0 && pendingSync != 0 && (ws->dStall ? VL_RANDOM_I(7) < 80 : 1) ){
top->dBus_sync_valid = 1;
}
#endif #endif
} }