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Fix Csr ReadWrite interration with DBusCachedPlugin execute halt

This commit is contained in:
Dolu1990 2020-11-16 12:37:48 +01:00
parent c1b0869c21
commit ba523c627a
1 changed files with 2 additions and 2 deletions
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4
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -1060,8 +1060,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
val readData = Bits(32 bits) val readData = Bits(32 bits)
val writeInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_WRITE_OPCODE) val writeInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_WRITE_OPCODE)
val readInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_READ_OPCODE) val readInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_READ_OPCODE)
val writeEnable = writeInstruction && ! blockedBySideEffects && !arbitration.isStuckByOthers val writeEnable = writeInstruction && !arbitration.isStuck
val readEnable = readInstruction && ! blockedBySideEffects && !arbitration.isStuckByOthers val readEnable = readInstruction && !arbitration.isStuck
val readToWriteData = CombInit(readData) val readToWriteData = CombInit(readData)
val writeData = if(noCsrAlu) writeSrc else input(INSTRUCTION)(13).mux( val writeData = if(noCsrAlu) writeSrc else input(INSTRUCTION)(13).mux(