Fix Csr ReadWrite interration with DBusCachedPlugin execute halt
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@ -1060,8 +1060,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
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val readData = Bits(32 bits)
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val writeInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_WRITE_OPCODE)
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val readInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_READ_OPCODE)
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val writeEnable = writeInstruction && ! blockedBySideEffects && !arbitration.isStuckByOthers
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val readEnable = readInstruction && ! blockedBySideEffects && !arbitration.isStuckByOthers
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val writeEnable = writeInstruction && !arbitration.isStuck
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val readEnable = readInstruction && !arbitration.isStuck
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val readToWriteData = CombInit(readData)
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val writeData = if(noCsrAlu) writeSrc else input(INSTRUCTION)(13).mux(
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