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VexRiscv
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Fix UserInterruptPlugin interrupt enable

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Dolu1990 2020-10-09 10:45:23 +02:00 committed by GitHub
parent 8bd1785233
commit bbaa0520c0
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1 changed files with 2 additions and 2 deletions
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4
src/main/scala/vexriscv/plugin/CsrPlugin.scala
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@ -1191,9 +1191,9 @@ class UserInterruptPlugin(interruptName : String, code : Int, privilege : Int =
interrupt = in.Bool().setName(interruptName)
val interruptPending = RegNext(interrupt) init(False)
val interruptEnable = RegInit(False).setName(interruptName + "_enable")
csr.addInterrupt(interruptPending , code, privilege, Nil)
csr.addInterrupt(interruptPending && interruptEnable, code, privilege, Nil)
csr.r(csrAddress = CSR.MIP, bitOffset = code,interruptPending)
csr.rw(csrAddress = CSR.MIE, bitOffset = code, interruptEnable)
}
override def build(pipeline: VexRiscv): Unit = {}
}
}