Add PmpPluginOld (support TOR)
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Dolu1990
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/*
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* Copyright (c) 2020 Samuel Lindemer <samuel.lindemer@ri.se>
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*
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* SPDX-License-Identifier: MIT
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*/
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package vexriscv.plugin
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import vexriscv.{VexRiscv, _}
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import spinal.core._
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import spinal.lib._
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import scala.collection.mutable.ArrayBuffer
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/* Each 32-bit pmpcfg# register contains four 8-bit configuration sections.
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* These section numbers contain flags which apply to regions defined by the
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* corresponding pmpaddr# register.
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*
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* 3 2 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | pmp3cfg | pmp2cfg | pmp1cfg | pmp0cfg | pmpcfg0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | pmp7cfg | pmp6cfg | pmp5cfg | pmp4cfg | pmpcfg2
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* 7 6 5 4 3 2 1 0
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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* | L | 0 | A | X | W | R | pmp#cfg
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* +-------+-------+-------+-------+-------+-------+-------+-------+
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*
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* L: locks configuration until system reset (including M-mode)
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* 0: hardwired to zero
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* A: 0 = OFF (null region / disabled)
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* 1 = TOR (top of range)
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* 2 = NA4 (naturally aligned four-byte region)
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* 3 = NAPOT (naturally aligned power-of-two region, > 7 bytes)
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* X: execute
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* W: write
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* R: read
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*
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* TOR: Each 32-bit pmpaddr# register defines the upper bound of the pmp region
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* right-shifted by two bits. The lower bound of the region is the previous
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* pmpaddr# register. In the case of pmpaddr0, the lower bound is address 0x0.
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*
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* 3 2 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | address[33:2] | pmpaddr#
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* NAPOT: Each 32-bit pmpaddr# register defines the region address and the size
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* of the pmp region. The number of concurrent 1s begging at the LSB indicates
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* the size of the region as a power of two (e.g. 0x...0 = 8-byte, 0x...1 =
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* 16-byte, 0x...11 = 32-byte, etc.).
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*
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* 3 2 1
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* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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* | address[33:2] |0|1|1|1|1| pmpaddr#
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* +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
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*
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* NA4: This is essentially an edge case of NAPOT where the entire pmpaddr#
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* register defines a 4-byte wide region.
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*/
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case class PmpRegister(previous : PmpRegister) extends Area {
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def OFF = 0
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def TOR = 1
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def NA4 = 2
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def NAPOT = 3
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val state = new Area {
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val r, w, x = Reg(Bool)
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val l = RegInit(False)
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val a = Reg(UInt(2 bits)) init(0)
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val addr = Reg(UInt(32 bits))
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}
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// CSR writes connect to these signals rather than the internal state
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// registers. This makes locking and WARL possible.
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val csr = new Area {
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val r, w, x = Bool
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val l = Bool
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val a = UInt(2 bits)
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val addr = UInt(32 bits)
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}
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// Last valid assignment wins; nothing happens if a user-initiated write did
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// not occur on this clock cycle.
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csr.r := state.r
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csr.w := state.w
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csr.x := state.x
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csr.l := state.l
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csr.a := state.a
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csr.addr := state.addr
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// Computed PMP region bounds
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val region = new Area {
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val valid, locked = Bool
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val start, end = UInt(32 bits)
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}
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when(~state.l) {
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state.r := csr.r
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state.w := csr.w
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state.x := csr.x
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state.l := csr.l
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state.a := csr.a
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state.addr := csr.addr
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if (csr.l == True & csr.a == TOR) {
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previous.state.l := True
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}
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}
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val shifted = state.addr |<< 2
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val mask = state.addr & ~(state.addr + 1)
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val masked = (state.addr & ~mask) |<< 2
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// PMP changes take effect two clock cycles after the initial CSR write (i.e.,
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// settings propagate from csr -> state -> region).
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region.locked := state.l
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region.valid := True
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switch(csr.a) {
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is(TOR) {
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if (previous == null) region.start := 0
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else region.start := previous.region.end
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region.end := shifted
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}
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is(NA4) {
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region.start := shifted
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region.end := shifted + 4
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}
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is(NAPOT) {
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region.start := masked
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region.end := masked + ((mask + 1) |<< 3)
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}
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default {
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region.start := 0
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region.end := shifted
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region.valid := False
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}
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}
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}
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class PmpPluginOld(regions : Int, ioRange : UInt => Bool) extends Plugin[VexRiscv] with MemoryTranslator {
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// Each pmpcfg# CSR configures four regions.
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assert((regions % 4) == 0)
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val pmps = ArrayBuffer[PmpRegister]()
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val portsInfo = ArrayBuffer[ProtectedMemoryTranslatorPort]()
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override def newTranslationPort(priority : Int, args : Any): MemoryTranslatorBus = {
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val port = ProtectedMemoryTranslatorPort(MemoryTranslatorBus(new MemoryTranslatorBusParameter(0, 0)))
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portsInfo += port
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port.bus
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}
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override def build(pipeline: VexRiscv): Unit = {
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import pipeline.config._
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import pipeline._
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import Riscv._
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val csrService = pipeline.service(classOf[CsrInterface])
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val privilegeService = pipeline.service(classOf[PrivilegeService])
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val core = pipeline plug new Area {
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// Instantiate pmpaddr0 ... pmpaddr# CSRs.
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for (i <- 0 until regions) {
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if (i == 0) {
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pmps += PmpRegister(null)
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} else {
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pmps += PmpRegister(pmps.last)
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}
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csrService.r(0x3b0 + i, pmps(i).state.addr)
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csrService.w(0x3b0 + i, pmps(i).csr.addr)
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}
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// Instantiate pmpcfg0 ... pmpcfg# CSRs.
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for (i <- 0 until (regions / 4)) {
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csrService.r(0x3a0 + i,
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31 -> pmps((i * 4) + 3).state.l, 23 -> pmps((i * 4) + 2).state.l,
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15 -> pmps((i * 4) + 1).state.l, 7 -> pmps((i * 4) ).state.l,
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27 -> pmps((i * 4) + 3).state.a, 26 -> pmps((i * 4) + 3).state.x,
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25 -> pmps((i * 4) + 3).state.w, 24 -> pmps((i * 4) + 3).state.r,
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19 -> pmps((i * 4) + 2).state.a, 18 -> pmps((i * 4) + 2).state.x,
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17 -> pmps((i * 4) + 2).state.w, 16 -> pmps((i * 4) + 2).state.r,
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11 -> pmps((i * 4) + 1).state.a, 10 -> pmps((i * 4) + 1).state.x,
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9 -> pmps((i * 4) + 1).state.w, 8 -> pmps((i * 4) + 1).state.r,
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3 -> pmps((i * 4) ).state.a, 2 -> pmps((i * 4) ).state.x,
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1 -> pmps((i * 4) ).state.w, 0 -> pmps((i * 4) ).state.r
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)
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csrService.w(0x3a0 + i,
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31 -> pmps((i * 4) + 3).csr.l, 23 -> pmps((i * 4) + 2).csr.l,
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15 -> pmps((i * 4) + 1).csr.l, 7 -> pmps((i * 4) ).csr.l,
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27 -> pmps((i * 4) + 3).csr.a, 26 -> pmps((i * 4) + 3).csr.x,
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25 -> pmps((i * 4) + 3).csr.w, 24 -> pmps((i * 4) + 3).csr.r,
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19 -> pmps((i * 4) + 2).csr.a, 18 -> pmps((i * 4) + 2).csr.x,
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17 -> pmps((i * 4) + 2).csr.w, 16 -> pmps((i * 4) + 2).csr.r,
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11 -> pmps((i * 4) + 1).csr.a, 10 -> pmps((i * 4) + 1).csr.x,
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9 -> pmps((i * 4) + 1).csr.w, 8 -> pmps((i * 4) + 1).csr.r,
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3 -> pmps((i * 4) ).csr.a, 2 -> pmps((i * 4) ).csr.x,
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1 -> pmps((i * 4) ).csr.w, 0 -> pmps((i * 4) ).csr.r
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)
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}
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// Connect memory ports to PMP logic.
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val ports = for ((port, portId) <- portsInfo.zipWithIndex) yield new Area {
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val address = port.bus.cmd(0).virtualAddress
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port.bus.rsp.physicalAddress := address
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// Only the first matching PMP region applies.
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val hits = pmps.map(pmp => pmp.region.valid &
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pmp.region.start <= address &
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pmp.region.end > address &
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(pmp.region.locked | ~privilegeService.isMachine()))
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// M-mode has full access by default, others have none.
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when(CountOne(hits) === 0) {
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port.bus.rsp.allowRead := privilegeService.isMachine()
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port.bus.rsp.allowWrite := privilegeService.isMachine()
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port.bus.rsp.allowExecute := privilegeService.isMachine()
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} otherwise {
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port.bus.rsp.allowRead := MuxOH(OHMasking.first(hits), pmps.map(_.state.r))
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port.bus.rsp.allowWrite := MuxOH(OHMasking.first(hits), pmps.map(_.state.w))
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port.bus.rsp.allowExecute := MuxOH(OHMasking.first(hits), pmps.map(_.state.x))
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}
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port.bus.rsp.isIoAccess := ioRange(port.bus.rsp.physicalAddress)
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port.bus.rsp.isPaging := False
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port.bus.rsp.exception := False
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port.bus.rsp.refilling := False
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port.bus.busy := False
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}
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}
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}
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}
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